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Giuli0

simulating time delays in SystemC

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Hello!

I am working on a SystemC project which has 2 different modules interacting through ports and channels. Both modules are running SC_THREADS. Now, I am having problems using the wait(sc_time) statement. What I want to do is simply to let the time flow (simulated systemC time) while I am inside one thread, without removing the process from the runnable set and without allowing another thread to resume (which happens if I use wait(sc_time)). I want to stay inside the thread, and I want the thread to "take some time" to execute. i need to to this because I am simulating a ram memory, and I want the memory_thread to take some time to execute, in order to emulate memory access delay. How can I do it?

 

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Your question doesn't make sense.. you do not seem to understand how SystemC scheduling works. It is not possible to insert a wait statement "without removing the process from the runnable set and without allowing other thread to resume". The converse of that statement is actually true - it is only when a SystemC wait statement gets executed that an other thread is allowed to resume (and the current thread yields).

 

The good news is, it is certainly possible to model memory delays with how the threads work in SystemC. It requires the modules to synchronize over the connected ports - so the 'memory' model will signal when the data is available, and the 'master' model should wait for that signal from memory.

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So, do you think that one solution could be for the memory_thread to notify another process waiting for it, and this one to notify back to the memory_thread, after the delay? Or maybe doing something better without using a third process, but still using these commands: event_name.notify(mem_delay)  and  wait(event_name)?

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Your question doesn't make sense.. you do not seem to understand how SystemC scheduling works. It is not possible to insert a wait statement "without removing the process from the runnable set and without allowing other thread to resume". The converse of that statement is actually true - it is only when a SystemC wait statement gets executed that an other thread is allowed to resume (and the current thread yields).

 

The good news is, it is certainly possible to model memory delays with how the threads work in SystemC. It requires the modules to synchronize over the connected ports - so the 'memory' model will signal when the data is available, and the 'master' model should wait for that signal from memory.

 

So, do you think that one solution could be for the memory_thread to notify another process waiting for it, and this one to notify back to the memory_thread, after the delay? Or maybe doing something better without using a third process, but still using these commands: event_name.notify(mem_delay)  and  wait(event_name)?

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So, do you think that one solution could be for the memory_thread to notify another process waiting for it, and this one to notify back to the memory_thread, after the delay? Or maybe doing something better without using a third process, but still using these commands: event_name.notify(mem_delay)  and  wait(event_name)?

 

There are two modules - one of them is clearly a memory. Let us call it 'memory':

class memory : public sc_module
{
   // ...
};

..And the other is reading from the memory, let us call it 'master':

class master : public sc_module
{
   // ...
};

Now, before we can look at solving your question, we need to define how 'master' and 'memory' communicate. One option is via plain signals, for example an APB-like interface (a poort choice for a memory, but easier to list the signals):

class master : public sc_module
{
   public:
      sc_out<uint32_t> paddr; // Address
      sc_out<uint32_t> pwdata; // Write data
      sc_in<uint32_t>   prdata; // Read data
      sc_in<bool> pready; // Ready signal from slave
      sc_in<bool> ptx_type; // Transfer type, read or write
      sc_out<bool> psel; // Select slave
};

// class memory has the inverse of the above set of ports: sc_in for sc_out and vice versa

The master class can start a 'write' transfer by writing the address and data on paddr/pwdata, and asserting the psel signal. Then, until the pready signal is asserted by memory, it has to wait. The memory will wait for required time (to simulate RAM access delay) before asserting pready:

void master_thread()
{
   // ...
   paddr = 0x1000;
   pwdata = 0x1234;
   psel = 1;
   wait(pclk.posedge_event()); // Wait for one clock to pass, to allow the slave to respond
   // Note: the exact number of clock cycles that the master has to wait depends on the bus protocol spec

   // Wait for slave: if it is not yet ready
   if(pready != 1) {
      wait(pready.posedge_event());
   }
   // ...
}

If the master-memory communication is with a TLM style higher level interface, then it is easier. Assuming a blocking API, it can be as simple as:

class master : public sc_module
{
   apb_tlm_port master_port; // TLM APB master port
   // ...
};

void master_thread(void)
{
   // ...
   // Function will only return when the slave has completed the write, after delays if applicable
   master_port.write(0x1000, 0x1234);
   // ...
}

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So, do you think that one solution could be for the memory_thread to notify another process waiting for it, and this one to notify back to the memory_thread, after the delay? Or maybe doing something better without using a third process, but still using these commands: event_name.notify(mem_delay)  and  wait(event_name)?

Hello Sir,

What you are attempting to do is the classic reader-writer problem - i.r., use shared

resource. I am afraid your best option would be to use some built-in concurrency

control scheme as sc_mutex. sc_semaphore. These constructs prevent the reader

from reading the sahred resource when the producer is writing to it, and vice-versa.

Very powerful tricks.

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