interfaces initialization inside internal module

[drianf0]

Hello,

The question is SystemVerilog specific, not related to UVM. I was wondering if it is possible to initialize an interface inside an internal module A and further pass it to an another module B, which is at the same level of hierarchy as the module A.

interface Inter (input logic clk);
  logic a;
endinterface

module A(Inter inter);
   logic clk;
   Inter  inter(clk);
endmodule

module B(Inter inter);
  always_ff @(posedge inter.clk)
    .....
endmodule
   

module top;  
  A a( .* );
  B b( .* );
endmodule

Let's assume module A is a master of some Stream interface (like AXI4-Stream), B is the slave. The signal clk could be a regular variable inside the Inter, however, clk must be connected to the interface, so it seems logical to me, that it's on the port list, so developer will not forget to provide it. Therefore (port assignment of inter), the inter has to be initialized inside the module A, not in top as it would be done in case of regular interface usage. The code is for synthesis and my compiler doesn't support virtual interfaces. Does it exist any elegant solution for the described issue ?

 

Thanks,

Adrian

[tudor.timi]

Hi Adrian,

 

Since you want to have clk as a port to the interface, the only idea I have at the moment is to do something like this:

interface Inter (inout logic clk);
  logic a;
  logic b;
  
  modport master(
    output clk,
    output a,
    input b
  );
  
  modport slave (
    input clk,
    input a,
    output b
  );
endinterface

module A(Inter.master inter);
   bit clk;
   always #1 clk = ~clk;
  
   assign inter.clk = clk;
endmodule

module B(Inter.slave inter);
  always_ff @(posedge inter.clk)
    $display("foo");  
endmodule
   

module top;
  Inter inter(clk);
  
  A a( .* );
  B b( .* );
endmodule

You have to instantiate the interface on top level to hold your bundle of wires and pass that to both your modules. We have declare clk as inout to be able to both read and write from/to it. You declare modports to restrict access to the signals. You want to only be able to drive the clock from the master, but not from the slave; same goes for the other signals that you don't define as ports (a is a master output/slave input and b is a slave output/master input). You can read more about modports here: http://www.asic-world.com/systemverilog/interface3.html.

 

You can also find the code on EDA Playground: http://www.edaplayground.com/x/rA.

[David Black]

Quick answer to the original question is "yes".

[kirloy]

interface Inter (input logic clk);

  logic a;

endinterface

module A();

   logic clk;

   Inter  inter(clk);

endmodule

module B(Inter inter);

  always_ff @(posedge inter.clk)

    ...

endmodule

   

module top;  

  A a(  );

  B b( a.inter );

endmodule