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what am i caution about delta time?

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Hi

As i know, combinational logic have delta time delay.

can i see real delta time delay in systemC?

Are there any examples?

what should i do to avoid delta time?

Are there any techniquies?

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SystemC primitive channels (sc_signal, sc_fifo etc) model delta cycles.

 

I'm not sure what you mean by "avoid delta time".

 

If you mean you don't want deltas to be used, write your models without primitive channels, and do not use any time delays. Your program will execute in zero time and have no deltas. If you use more than one SC_METHOD it will also most likely be non-deterministic.

 

If you mean how to avoid the effects of deltas, just use a clock like you would in RTL design.

 

regards

Alan

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SystemC primitive channels (sc_signal, sc_fifo etc) model delta cycles.

 

I'm not sure what you mean by "avoid delta time".

 

If you mean you don't want deltas to be used, write your models without primitive channels, and do not use any time delays. Your program will execute in zero time and have no deltas. If you use more than one SC_METHOD it will also most likely be non-deterministic.

 

If you mean how to avoid the effects of deltas, just use a clock like you would in RTL design.

 

regards

Alan

I meant that i can see delta time delay in simulator in rtl during sdf annotation.

Or when i forcing to # delay to wire in rtl, i can see that too.

But normally circumstance in rtl, it does not show about delta time delay without # delay.

Does make it sense?

That's it, can i think that they have same concepts for delta time?

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The delays you seen after SDF annotation are not delta delays, they are real (modelled) amounts of time.

 

In RTL you don't see the delta delays on waveforms normally (tools can show them to you if you want), but the deltas are there, and it is possible to write bad code by ignoring the deltas. A good example would be to create a copy of a clock signal using a signal assignment in VHDL - you'll then get hold time violations if you clock flip-flop models off the original and delta-delayed clock.

 

SystemC does have delta cycles if you use primitive channels (sc_signal/sc_fifo), but there's no built-in way of modelling SDF back annotation.  

 

You wouldn't use SystemC for that, you'd use Verilog or VHDL/VITAL.

 

regards

Alan

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The delays you seen after SDF annotation are not delta delays, they are real (modelled) amounts of time.

 

In RTL you don't see the delta delays on waveforms normally (tools can show them to you if you want), but the deltas are there, and it is possible to write bad code by ignoring the deltas. A good example would be to create a copy of a clock signal using a signal assignment in VHDL - you'll then get hold time violations if you clock flip-flop models off the original and delta-delayed clock.

 

SystemC does have delta cycles if you use primitive channels (sc_signal/sc_fifo), but there's no built-in way of modelling SDF back annotation.  

 

You wouldn't use SystemC for that, you'd use Verilog or VHDL/VITAL.

 

regards

Alan

So is delta time any affect to systemC simulation?

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SystemC does not support SDF modelling.

SystemC does have simulation deltas if you use primitive channels.

Alan

As i know, when i use sc_signal , systemc have simulation deltas.

But i not sure deltas. Where or how can i find deltas? and in tool?

Would you means that deltas have same meanning between blocking and non blocking?

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SystemC keeps a count of the total number of delta cycles. You can find it out with the function sc_delta_count().

 

Deltas are kind of similar to non-blocking verilog assignments.

 

Blocking assignments in Verilog are like standard C++ variable assignments.

 

regards

Alan

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