uvm component name constraints

[cbriggs]

We've been using UVM 1.1d. Now we're testing 1.2 and after cleaning up some other things we're getting warnings like this:

the name "sso_aw_tb_top.sso_aw_wrapper_i.sso_aw.aw_csr.aq.aq_thr_port" of the component "uvm_test_top.ssoaw_env.mem_env.sso_aw_tb_top.sso_aw_wrapper_i.sso_aw.aw_csr.aq.aq_thr_port" violates the uvm component name constraints

This warning comes from base/uvm_traversal.svh and appears to be from a change put in for Mantis 4712. There's a comment in the Mantis that this was discussed and there was not unanimous agreement to get this into 1.2.

So the first question is this: if this wasn't approved for 1.2, why is it in 1.2?

More important to me is this: is this likely to be approved in the foreseeable future? If it is, we'll clean up our names. If not, I'm inclined to hack the regex to allow dots.

 

For background info, the vast majority of our object names do not include the full hierarchy. For BIST and ECC testing, we have our memories instrumented to push their full hierarchical name onto a list and from that list we create an analysis port for each one, and the full name is passed in with "_port" when we new the port. We can't just strip it down to the memory name because they're not unique, which is why the full hierarchical name seemed like a good idea at the time.

 

Thanks.

[uwes]

hi,

 

mantis4712 was approved in a followup meeting. i would need to dig the meeting notes if this is of interest.

 

the warning has been created to ensure a unique and translation between component and its location in the component tree. at best you just face printing/debug problems in the worst case other facilities could get confused.

 

you got a couple of options  

 

- you create the component hierarchy as necessary. all you need is the tree

- you shutdown the warning

- you override the regex and provide an own check pattern

 

/uwe