Jump to content
Sign in to follow this  

Difference between uvm_hdl_force and uvm_hdl_deposit

Recommended Posts



a "force" will preserve the value on the reg/wire until you "release" the force. a value you just "deposit" will be overwritten by any subsequent value updates/assignments.



Share this post

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
Sign in to follow this