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jsmith125x

SystemC analog co-simulation

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Hi,

 

If I understand it correctly you want to co-simulate SystemC + Some AMS Language.

 

My first question will be what is this "Some AMS Language" ?

 

There are two problems in general you will be solving:

 

  • data exchange
  • simulator time synchronization.

 

If you are unlucky, then you possibly need to handle analog simulator timing back stepping problem.

 

Please let me know what is the analog Language and/or Simulator.

 

Regards, 

Sumit

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In our VHDL engine we are creating rollback points during simulation. This saves all VHDL data (incremental), including process states, stacks, signals, time etc. When the analog engine requires rollback (because of convergence problem), the VHDL engine select the proper rollback point and restores the whole engine to this point (process states, stacks, signals, time etc). 

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Hi,

 

If I understand it correctly you want to co-simulate SystemC + Some AMS Language.

 

My first question will be what is this "Some AMS Language" ?

 

There are two problems in general you will be solving:

 

  • data exchange
  • simulator time synchronization.

 

If you are unlucky, then you possibly need to handle analog simulator timing back stepping problem.

 

Please let me know what is the analog Language and/or Simulator.

 

Regards, 

Sumit

Hello Sir,

As Sumit has pinpointed the issue, one has to decide on the analog langauge.

As SystemC-AMS has been developed closely linked with SystemC, it would

be a natural choice, as it eliminates the data output format and synchronization

issues.

However, if the choice is e.g., Verilog-AMS, then first of all, there are no open

source POC simulators, and the data output format is proprietary. A crude way

to use this would be to write the output to a text file, ensure that the format is

compatible for the SystemC simulator and then run SystemC simulator. This 

I know from personal experience.

Hope that helps.

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(1) The SystemC-AMS engine how handle the timing back stepping problem?
 
(2) 

A crude way

to use this would be to write the output to a text file, ensure that the format is

compatible for the SystemC simulator and then run SystemC simulator

 

Could you write it in detail? How can this method handle the timing back stepping problem?

 
PS. Im using the SystemC simulation in dll mode. I created a dynamically allocated instance of top module. sc_start called from the analog engine directly, and the SystemC simulation is paused when an output port changes.
 
I can't login with my previous account, I don't know why..

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You are unlucky but not out of option. 

 

I see two big work are already done:

  • data exchange
  • simulator time synchronization.

You can surely make them working for SC.

 

Okay on the next big thing, timing back stepping:

 

Couple of years back I read in some papers published by Prof. Tom Kazmierski's group of Southampton University who works on a analog language called SystemC-A, where they either presented logic that simulator back-stepping is not needed for analog simulator interfacing SC OR SC is not needed to back-step - I do not exactly remember that. Search that paper for yourself. 

 

If analog simulator back-stepping is not needed (I will be very uncomfortable with this idea) then you can force your analog simulator to a linear solver like backward Euler and go ahead with it. In any case, they must have published a paper where they talked about this issue. Check it out.

 

Regards,

Sumit

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Indeed, rollback is very difficult to realize in SystemC. It would require user's to follow very strict coding guidelines, which will be hard to check by the SystemC kernel and can thus easily silently broken by user's. However, you need rollback capability in SystemC only if your home-grown simulator is to be considered the co-simulation master, which imposes the timing constraints on the discrete-event simulation kernel of SystemC. If you make SystemC the master, things will get easier. With IEEE Std 1666-2011, new functions were introduced to facilitate co-simulation by allowing to query the state of the simulation kernel, including the time point of the next event. In addition the simulation control has been improved. Future versions of the SystemC standard may enable even finer interactions with the different elaboration and simulation phases using additional callbacks, as presented by Philipp A. Hartmann from OFFIS at the ESCUG 2013 meeting: "Modelling, simulation, and advanced tracing for extra-functional properties in SystemC/TLM". There has been much work on co-simulation with SystemC, which you can dig up via a web search. Note, SystemC AMS does sidestep the problem by using a synchronous-data-flow-based synchronization mechanism for interaction with SystemC and disallowing any back-stepping (only zero time steps have been allowed since SystemC AMS 2.0 for relaxation).

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(1)

The analog engine is our analog engine (SPICE basically). The VHDL and analog co-simulation is working properly. Now we'd like to extend to handle SystemC digital models. Our co-simulation engine uses rollback currently.

 

(2)

This engine uses rollback also?

http://www.systemc-ams.org/

Hi, i am also working on the interface of spice & VHDL co-simulation.But still facing some problems.Could you plz share work or guide me for this work.It will be of great help to me.The spice engine i am using is ngspice &  for VHDL simulation GHDL being used.

 

Thanks,

Manas

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Hi, i am also working on the interface of spice & VHDL co-simulation.But still facing some problems.Could you plz share work or guide me for this work.It will be of great help to me.The spice engine i am using is ngspice &  for VHDL simulation GHDL being used.

 

Thanks,

Manas

 

Which problem do you have? But this topic is SystemC.

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In of your posts you have mentioned that you have alredy done the co-simulation of spice and vhdl.

I want to know about that as i am stuck at what format of data input will be given to GHDL and

also how the output from GHDL will be taken and given as input to ngspice for co-simulation.

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In of your posts you have mentioned that you have alredy done the co-simulation of spice and vhdl.

I want to know about that as i am stuck at what format of data input will be given to GHDL and

also how the output from GHDL will be taken and given as input to ngspice for co-simulation.

 

Im not familiar with GHDL and ngspice. My old account is disabled (125x)

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I find this in systemic-ams v0.15 white paper:

 

 

Increasing time only, no backtracking: In the simulation of analog and mixed-signal systems, it is a common technique to synchronize different simulators only when this is really needed. This can lead to a situation, where an event from one simulator occurs, which is in the past for other simulators. Then, a rollback mechanism could set the simulation time back to a point in the past. However, this requires the ability to save a state and to restore the saved state. This is not supported by SystemC, and the synchronization layer therefore can only increase the time. 

 

 

 

This paper might be helpful: A SystemC/Simulink Co-Simulation Framework for Continuous/Discrete-Events Simulation (http://goo.gl/16qXBl). They work out a method to avoid rollback by predicting events. Maybe you can contact the author for the code.

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