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karandeep963

Constraining Sequencer from testcase

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Hi ,

 

Sorry the heading should be Constraint Sequence from testcase

 

I am unable to change it , seen after posted

 

I am wondering to constrain my sequence from testcase, is there any good way of doing it ?

----------------------------Test Code----------------------------------------------\\
class card_test extends uvm_test;

task run_phase(uvm_phase phase);
    card_seq card_seq_i;
    repeat(3) begin
      phase.raise_objection(.obj(this));
      card_seq_i = card_seq::type_id::create(.name("card_seq_i"), .contxt(get_full_name()));
      //assert(card_seq_i.randomize());// actual test case
      //assert(card_seq_i.randomize() with { card_seq_i.pkt_state == READY;}); // dedicated test
      `uvm_info("card_test", { "\n", card_seq_i.sprint() }, UVM_LOW)
      card_seq_i.start(card_env_i.card_agent_e.m_sequencer);
      #10ns ;
      phase.drop_objection(.obj(this));
	end
   endtask: run_phase

The line 09 and 10 if chosen gives me error.

 

Thanks for help

 

Regards,

KS 

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It is always a good idea to show us the complete error message, not just say you got an error. I'm assuming you got an assertion error, which means randomization failed.
We can't know why without seeing your constraints.

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Hi Dave,

 

My apologizes for the same , below is the code snippet and errors:

class gift_boxed_jelly_beans_sequence extends uvm_sequence#(jelly_bean_transaction);
   rand int unsigned num_jelly_bean_flavors; // knob

   constraint num_jelly_bean_flavors_con { num_jelly_bean_flavors == 10; }

   function new(string name = "");
      super.new(name);
   endfunction: new

   task body();
      same_flavored_jelly_beans_sequence jb_seq;
      repeat (num_jelly_bean_flavors) begin
	 jb_seq = same_flavored_jelly_beans_sequence::type_id::create(.name("jb_seq"), .contxt(get_full_name()));
	 assert(jb_seq.randomize());
//	 `uvm_info("gift_boxed_jelly_beans_sequence", { "\n", jb_seq.sprint() },
//		   UVM_LOW)
	 jb_seq.start(m_sequencer);
      end
   endtask: body

   `uvm_object_utils_begin(gift_boxed_jelly_beans_sequence)
      `uvm_field_int(num_jelly_bean_flavors, UVM_ALL_ON)
   `uvm_object_utils_end
endclass: gift_boxed_jelly_beans_sequence
class jelly_bean_test extends uvm_test;
   `uvm_component_utils(jelly_bean_test)


task run_phase(uvm_phase phase);
      gift_boxed_jelly_beans_sequence jb_seq;

      phase.raise_objection(.obj(this));
      jb_seq = gift_boxed_jelly_beans_sequence::type_id::create
	       (.name("jb_seq"), .contxt(get_full_name()));
      assert(jb_seq.randomize() with { jb_seq.num_jelly_bean_flavors == 1;});
      `uvm_info("jelly_bean_test", { "\n", jb_seq.sprint() }, UVM_LOW)
      jb_seq.start(jb_env.jb_agent.jb_seqr);
      #10ns ;
      phase.drop_objection(.obj(this));
   endtask: run_phase
   
endclass: jelly_bean_test
UVM_INFO @ 0: reporter [RNTST] Running test jelly_bean_test...
      assert(jb_seq.randomize() with { jb_seq.num_jelly_bean_flavors == 1;});
                            |
ncsim: *W,SVRNDF (./jelly_bean_ex.sv,483|28): The randomize method call failed.
Observed simulation time : 0 FS + 33
ncsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints:

      assert(jb_seq.randomize() with { jb_seq.num_jelly_bean_flavors == 1;}); (./jelly_bean_ex.sv,483)
   constraint num_jelly_bean_flavors_con { num_jelly_bean_flavors == 10; } (./jelly_bean_ex.sv,182)
ncsim: *W,RNDOCS: These variables contribute to the set of conflicting constraints:

rand variables:
       num_jelly_bean_flavors [./jelly_bean_ex.sv, 180]

ncsim: *E,ASRTST (./jelly_bean_ex.sv,483): (time 0 FS) Assertion worklib.jelly_bean_pkg::jelly_bean_test::run_phase.__assert_6 has failed 
UVM_INFO jelly_bean_ex.sv(484) @ 0: uvm_test_top [jelly_bean_test] 

For the sake of reading I have placed only the sequence, test and error above . The full example is available at 

 

http://cluelogic.com/2011/07/uvm-tutorial-for-candy-lovers-transactions-and-sequences/

 

Hope this time i am able to provide my problem clearly

 

Thanks,

KS

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hi,

 

the error message clearly indicates what is wrong:

 

  1. ncsim: *W,RNDOCS: These constraints contribute to the set of conflicting constraints:
  2.  
  3. assert(jb_seq.randomize() with { jb_seq.num_jelly_bean_flavors == 1;}); (./jelly_bean_ex.sv,483)
  4. constraint num_jelly_bean_flavors_con { num_jelly_bean_flavors == 10; } (./jelly_bean_ex.sv,182)

 

num_jelly_bean_flavours cant be one and ten at the same time. 

 

/uwe

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uwes,

 

Thanks for replying, but can you tell how to resolve the error ????

 

I am basically overwriting a constraint from testcase.

 

I want it to have the value that is supplied from testcase.

 

So how does it creates conflict for two , test is obvious at high hierarchy so it can overwrite.

 

Please correct me if I am wrong .

 

:)

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You can override constraints in a class hierarchy, but that's not what you're doing.

 

e.g.

    class a;
        int i;
        constraint c { i == 10; }
   endclass

  class b extends a;
      constraint c { i == 1 };
  endclass

Note the constraints have the same name and are in a class hierarchy, so the class b constraint replaces the one in class a.

 

SV 2012 introduced soft constraints (constraints that will lose if in conflict with another strong constraint).

 

regards

Alan

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Thanks Alan,

 

But I was wondering to override the constraints for testclass itself , for which I have now made many sequence_item and override one sequence_item  by other sequence_item in build phase of the test.

 

While the constraints are overrided in the sequences , for which i have to create many sequences with different constraints (I need).

 

Which I don't want. 

 

I wish I could do it like : 

 

testclass -> randomise any sequence -> with constraints supplied from here.

 

but it does not work

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One way to do it would be to make your base class constraint very wide, then narrow it down with extra constraints (thus avoiding a conflict). E.g.

 

 constraint c { i > 0 && i < 1000;}

 

You can then constrain to any value within 0 to 1000 without a conflict.

 

Alternatively you could use variables. There's nothing to stop you saying

rand int unsigned num_jelly_bean_flavors; // knob
constraint num_jelly_bean_flavors_con { num_jelly_bean_flavors == j; }

and then constraining j from outside the class.

 

Alan

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If the sequence constraints are set up properly you could also disable the conflicting constraint on the sequence from the testcase.  This works best if the constraints are set up to only affect a single property because otherwise you need to recreate the constraints on the rest of the properties (your simple example demonstrates this).  For example, this would work:

jb_seq = gift_boxed_jelly_beans_sequence::type_id::create(.name("jb_seq"), .contxt(get_full_name()));

jb_seq.num_jelly_bean_flavors_con.constraint_mode(0);
assert(jb_seq.randomize() with { jb_seq.num_jelly_bean_flavors == 1;});

 

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You may want to look at the new soft constraint feature of SV1800-2012. A soft constraint is automatically disabled when there is a conflicting constraint. However, then you lose a way of describing your intent. Did you intend to disable the constraint with a new one, or did you add a conflicting constraint by mistake and now you will no longer get an constraint failure.

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hi Karandeep,

 

you can do one more thing.

 

you can use following approach,

 

`uvm_create(seq);

seq.<constraint_name>.constrant_mode(0)

seq.jelly_bean = 1.

seq.strat(seqr_name)

 

In this case you need to overwrite the constraint, and not required to even extend the class

 

hope this will help you

 

 

 

 

 

 

 

code may not be executable

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