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Resetting a randc permutation sequence
(See attached page from 1800-2012 SystemVerilog spec.)
 
   function bit [16:0] get_reasonable_buggy_data(bit [(A_SIZE-1):0] rid);
      string where="buggy";
//    randc unsigned int picky;  //random-cyclical variable  DECLARED ABOVE IN CLASS, SUCH
//    void'(randomize(pick) with {pick==1;}); FAILED-ATTEMPT to recompute permutation sequence
      
      for (int i=0; i<4; i++) begin
	 if (!randomize(picky) with {picky>=0; picky<4;}) begin `uvm_fatal("FAIL","") end

         `uvm_info(where,$psprintf("i=%0d picky=%0d data[1:0]=%2b",i, picky, rdata_set[picky][1:0]),UVM_HIGH)
         if ( rdata_set[picky][1:0] == 2'b11 ) begin 
            `uvm_info(where,$psprintf("     data[1:0]=%2b. GOT IT!",i, rdata_set[picky][1:0]),UVM_HIGH)
            return(rdata_set[picky]);  //exit random-cyclical sequence here. How to start it over?
         end
      end
      `uvm_fatal(where,$psprintf("After cycling thru entire memory model, did not find data desired"))
   endfunction
In a function, I am cycling thru the randomized values of a randc variable, "picky", which is used as an index.  I find what I am looking for and stop, not completing the cycle thru all the possible values of the variable, in a given permutation sequence.
Returning to this function, the randomization of the randc, picks up where the previous permutation sequence left off.  This makes sense.  This is undesirable here and leads to problems**.  I want to reset the randc permutation sequence, but am not sure if I am just not doing it properly or if my simulator does not support it properly.  (I can ask the simulator vendor about the latter.  I am inquiring here about the former.)
 
 
Problem details: 
The randc variable "picky" can have 4 values: 0,1,2,3.
We call the above function 3 times. Each time we want to use picky as an index to randomly search a memory of size 4, stopping when we find what we want.
 
Permutation sequences of picky are:
1st:   0,2,3,1
2nd:  3,0,1,2
3rd:  0,....           //final 3 are irrelevant and sim dies before we get to them
 
First time function is entered, we select '0','2',and '3' and find the goal in #3 and function returns.
Second time we finish off the 1st permutation with '1' and go into 2nd with '3', and have found what we want in #3. Function returns.
Third time, we finish the 2nd permutation with '0', '1', '2', and continue into the 3rd with '0'.  Function fails.  So, we did not get the randc effect we wanted, we never got to #3.
 
Even though we were iterating 4 times, once for each memory location and using a randc, we got a duplicate, b/c our randomization straddled two permutation sequences.  As such, we never found #3.
 

 

Print output from simulation:

[buggy] i=0 picky=0 data[1:0]=00
[buggy] i=1 picky=2 data[1:0]=00
[buggy] i=2 picky=3 data[1:0]=11
[buggy]      data[1:0]=10. GOT IT!3
[buggy] i=0 picky=1 data[1:0]=00
[buggy] i=1 picky=3 data[1:0]=11
[buggy]      data[1:0]=01. GOT IT!3
[buggy] i=0 picky=0 data[1:0]=00
[buggy] i=1 picky=1 data[1:0]=00
[buggy] i=2 picky=2 data[1:0]=00
[buggy] i=3 picky=0 data[1:0]=00
[buggy] After cycling thru entire memory model, did not find data desired
 
Note, this is a contrived example. I could allow all permutation sequences to complete or resolve this another way.  Based upon the description in the spec page attached, I tried to reset the permutation sequence by inserting the line labelled "FAILED-ATTEMPT".  Is that how resetting a permutation sequence should work?
 
 
 
Note: I am using IUS 13.10-s006
 
post-2891-0-45138100-1387309856_thumb.png

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