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Equivalence of bit duplication from Verilog in SystemC

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Hi all, 


I am a user of Verilog all the while, and I am currently looking into raising abstraction level of digital system design. To start off with, I am trying to convert a project written originally in Verilog into SystemC, and then try to synthesize back from SystemC into Verilog to see the synthesis performance.


I am currently stuck with bit duplication in SystemC. For example, in Verilog, we can do bit duplication by using the syntax below:


 output[15:0] = {8{d[8]}, d[7:0]}


I know that SystemC allow for concatenation. However, duplication using 8(d[8]) seem doesn't work in SystemC. Any advice?

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I am actually trying to develop a simple microprocessor from SystemC into synthesizable verilog code. The verilog code that shows the need to implement the idea of sign extension is as below:


 output[15:0] = word? d[15:0] : {8{d[8]}, d[7:0]};


To my knowledge, the datatype declaration for SystemC must be determined at compile time right? i.e. we cannot declare the datatype for d in the verilog as sc_int<8> or sc_int<16>, which is depending on the control signal "word".

Hence, in this case, how do we write in SystemC in order to get the corresponding synthesized verilog code?

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I'd assume from your code that you're not actually *declaring* d based on word, in the Verilog d is presumably declared as reg [15:0].


You could write equivalent functionality using an if, e.g.

sc_int<16> d, output;

void make_output () { // register as an SC_METHOD
    for (int i = 0; i<15; i++)
      output[i] = d[8];
    if (word)
       output = d;
       output[7:0] = d[7:0];




P.S. There may be an easier way, I just can't think of it at the moment :-)

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