UVM Phase issue

[akshaykasodariya]

Hi UVM Experts,

 

I am facing some issue with UVM phase. I have registered one sequence to pre_configure phase of one sequencer which is doing some chip configuration.

In my base test pre_configure phaseI am waiting for that configuration to get over usng hierarchy of RTL path signal. RTL takes some time after configuration gets over to toggle the indication of chip ready which i am waiting in base test pre_configure phase. I observe that sequence gets over but immediately test also gets finished even i raised the objection from base test pre_configure phase.

 

Would you please point me if it is exptected? I think till all raised objections are not lower simulation will not be over. and I want my test to wait once sequence is over and RTL toggles ready signal.

 

Thanks in advance for your time.

 

Thanks,

Akshay

 

[akshaykasodariya]

Just to add more information I dont have any more sequence registered for any agent after pre_configure sequence.

[mastrick]

Can you show some of the code you have for the base test pre_configure phase, including the raising of the objection?

[akshaykasodariya]

Hi Mastrick,

 

Code snap is like below

 

virtual task pre_configure_phase (uvm_phase phase);
    phase.raise_objection(this);
    `uvm_info (get_name(), $psprintf("Executing pre_configure phase of  my_base_test."), UVM_INFO)   


    while ( <hierarchy of rtl path> !== 1'b1 ) begin
    repeat(1)  @ (posedge clock);
    end
    .

    .

    .

    `uvm_info (get_name(), $psprintf(" Done Executing pre_configure phase of  my_base_test."), UVM_INFO)     
    phase.drop_objection(this);
  endtask : pre_configure_phase 

[akshaykasodariya]

I found the issue.

 

There was program block as a component in top and it was compeleting it's job so simulation was going down. So next phase was not getting time to end.

Thanks a lot

 

- Akshay