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Don't care bit handling in UVM RAL

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Not sure do you have similar problem? I have a problem in handling the reset value in RAL.

f the reset value of a field in the register is don't care, what can I do for it?

Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked.

Do you guys think it is a feasible way? Thanks.

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