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How to import a VHDL constant in system verilog

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I want to use a value which is a constant in my VHDL design file. I want to make my env. generic depending on the value of this constant. How do i import this constant from VHDL to SV




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the sv lrm requires to have these things declared in sv itself. there can be no explicit or implicit dependencies to definitions outside of the sv lrm world (well apart from dpi). if your simulator vendor supports the use of symbols from outside of the sv domain like vhdl then its a private extension, with a private semantic and with private functionality. 


a much better route in my mind is 


(A) translate the vhdl constant package/file to a sv constant package/file via a translator/generator or

(B) describe the constants in a language independent format and generate VHDL and SV from this common source.


both paths are simple, vendor independent, lrm compatible 




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