Why SystemC and who uses it ???

[karandeep963]

Hello All,

 

I know it sounds very odd "Why SystemC and who uses it ???".

 

But yes its true, I really want to know this.

 

Since I have heard a lot for SystemC, do understand it, learned and explored through this board, but not able to find its application.

 

SystemC features conveyed:

 

1. It can be used for architectural exploration : My question is how ?

2. For software , hardware co-simulation : I want to know how ?

 

There is nothing concrete available which could demonstrate the complete flow nor any example.

There is nothing which could support or prove the above quotes.

There is nothing that could give an approach that should be carried to execute any project.

 

After a hard search for the same, I came to know that it has been used in R&D for Image processing Product Development. But unfortunately not able to find how? 

 

I do found that VLSI industry is welcoming SystemC , but again how and in which way?

 

Does SystemC is a dream?

 

One could understand and practice SystemC using LRM, this board etc, but I cant find a place to execute the real project.

 

So, let me know "Why SystemC and who uses it ???"

 

 

"I really appreciate the efforts of the people active on this board, since many like me tasted the flavor of SystemC, develop there interest in SystemC, learned through the best personalities".

 

 

[apfitch]

Hi Karandeep,

 

   the main usage of SystemC is in design of large SoC. As such, it is mainly used by large semiconductor companies.

 

Typically such a company may be developing a large chip (very large!). That causes a number of problems

 

How to concurrently develop software and hardware?

How to start writing software drivers before the RTL design is finished?

How to develop a reference model to be used in with Testbench Automation/Constrained Random Verification environments?

How to build and re-use IP models for use in a high level model? (otherwise every company has to build processor models, bus fabric models etc from scratch).

If developing a completely new chip, how to analyse bus bandwidths, data flows and so on - especially with multiple processors competing for bus resource.

 

SystemC allows a company to attack all these problems - by building a model with accurate register modelling, the model may be used for software device driver development. Typically using very fast processor models and loosely timed styles, that model can boot multiple pieces of software on processor models at high speed.

 

With some refinement, a similar model can be used as a reference for TBA/CRV. You need a reference model, so why not re-use it?

 

For architectural analysis an approximately timed model is better suited - but remember you might not need it if you are refining an existing platform rather than starting from scratch.

 

For re-usable models - that's the point of TLM2, to create a standard API to allow exchange of models. Existing APIs (SCML, TAC etc) can gradually migrate to a standard, promoting re-use.

 

Finally why SystemC? Why not use SystemVerilog; or Java; or Python; or Haskell; or <fill in your favourite language here>?

 

There are many factors, some practical, some political, some historical.

 

In my opinion the main factors are/were

 

1. System Architects speak C++ / Excel / Word /Matlab. They don't speak Verilog/SystemVerilog/VHDL

 

2. SystemC started in 1999

 

3. EDA vendors got behind SystemC and developed tools to allow virtual platforms to be built

 

I hope that helps,

 

regards

Alan

 

P.S. Regarding finding references / information/ facts, the key point to remember is that the world of SoC/VLSI design is small. There just aren't many companies with the resources to develop large chips; and within those companies, there just aren't many system architects / modellers. In a typical large chip development they'll probably be many software engineers - probably considerably more than hardware engineers; within hardware, they'll be a few back-end people; a reasonable number of RTL designers; a similar or larger number of verification engineers; and perhaps 1 system architect. So SystemC just isn't used by large numbers of people, compared the Verilog/VHDL/SystemVerilog.

[apfitch]

By the way, it's worth reading Harry Foster's blog posts on Functional Verification - though he hasn't got to languages yet.

 

http://blogs.mentor.com/verificationhorizons/blog/2013/07/15/part-5-the-2012-wilson-research-group-functional-verification-study/

 

regards

Alan

[amitk3553]

Hi Karandeep,

 

   the main usage of SystemC is in design of large SoC. As such, it is mainly used by large semiconductor companies.

 

Typically such a company may be developing a large chip (very large!). That causes a number of problems

 

How to concurrently develop software and hardware?

How to start writing software drivers before the RTL design is finished?

How to develop a reference model to be used in with Testbench Automation/Constrained Random Verification environments?

How to build and re-use IP models for use in a high level model? (otherwise every company has to build processor models, bus fabric models etc from scratch).

If developing a completely new chip, how to analyse bus bandwidths, data flows and so on - especially with multiple processors competing for bus resource.

 

SystemC allows a company to attack all these problems - by building a model with accurate register modelling, the model may be used for software device driver development. Typically using very fast processor models and loosely timed styles, that model can boot multiple pieces of software on processor models at high speed.

 

With some refinement, a similar model can be used as a reference for TBA/CRV. You need a reference model, so why not re-use it?

 

For architectural analysis an approximately timed model is better suited - but remember you might not need it if you are refining an existing platform rather than starting from scratch.

 

For re-usable models - that's the point of TLM2, to create a standard API to allow exchange of models. Existing APIs (SCML, TAC etc) can gradually migrate to a standard, promoting re-use.

 

Finally why SystemC? Why not use SystemVerilog; or Java; or Python; or Haskell; or <fill in your favourite language here>?

 

There are many factors, some practical, some political, some historical.

 

In my opinion the main factors are/were

 

1. System Architects speak C++ / Excel / Word /Matlab. They don't speak Verilog/SystemVerilog/VHDL

 

2. SystemC started in 1999

 

3. EDA vendors got behind SystemC and developed tools to allow virtual platforms to be built

 

I hope that helps,

 

regards

Alan

 

P.S. Regarding finding references / information/ facts, the key point to remember is that the world of SoC/VLSI design is small. There just aren't many companies with the resources to develop large chips; and within those companies, there just aren't many system architects / modellers. In a typical large chip development they'll probably be many software engineers - probably considerably more than hardware engineers; within hardware, they'll be a few back-end people; a reasonable number of RTL designers; a similar or larger number of verification engineers; and perhaps 1 system architect. So SystemC just isn't used by large numbers of people, compared the Verilog/VHDL/SystemVerilog.

It means SystemC is of usage at architect level.

 

If I talk about at the level of design engineer:

 

I have already designed or to design some IP in any HDL language like VHDL,verilog.

 

Then what is the use of systemC at this level 

 

 

Regards

cam

[apfitch]

Hi Cam,

  there is use of SystemC at design level, because it is used by such as synthesis tools (such as Forte Design Systems Cynthesizer, or Xilinx Vivado HLS - other tools are also available).  I forgot to mention that above,

 

regards

Alan

[amitk3553]

Hi Cam,

  there is use of SystemC at design level, because it is used by such as synthesis tools (such as Forte Design Systems Cynthesizer, or Xilinx Vivado HLS - other tools are also available).  I forgot to mention that above,

 

regards

Alan

Hi Alan,

 

Means SystemC is synthesizable?

 

If I develop some IP in SystemC, through these tools, I will get gate level(netlist) of IP from systemC design?

 

 

Thanks

cam

[apfitch]

There's a draft Synthesisable Subset of SystemC standard on the Accellera website, see

 

http://www.accellera.org/downloads/drafts_review/

 

A tool that synthesizes SystemC might produced RTL Verilog/VHDL as an output, or it might produced a netlist - that depends on the tool. You'd need to ask the tool vendors,

 

regards

Alan