Free systemverilog/uvm simulator for small amounts of code exists?

[ljepson74]

Is there any free systemverilog simulator (w/ UVM support) for small amounts of code?

i.e. perhaps a vendor offers the license for free, to hook newbies and students, restricting them to less than 1000 lines of code or something?

[ljepson74]

Anyone?

[apfitch]

I don't think there is such a thing.

 

The Altera Modelsim Starter Edition is free, and supports some SystemVerilog (design constructs), but not classes/UVM/constrained random...

 

regards

Alan

[dave_59]

I don't think there is such a thing.

 

The Altera Modelsim Starter Edition is free, and supports some SystemVerilog (design constructs), but not classes/UVM/constrained random...

That's not completely correct. The Starter/Student editions will support classes. but not calls to class.randomize(), covergroups, or assertions. So you could create some basic UVM structures.

[apfitch]

Sorry Dave, I misunderstood...

 

regards

Alan

[sri205]

Hi Dave,

 

As a novice, from the tutorials, all i can remember is, it is necessary to register component using system calls liks `uvm_component_utils or something similar. Now, If i take up a student version of modelsim, it doesn't come with any uvm_library's binary info. So, how can i register any uvm components/objects/sequences and use it?

 

Thanks.

[dave_59]

You will have to download the UVM kit from the Accellera site and compile it yourself. I don't recall if the student version supports DPI, so you may need to compile it with +define+UVM_NO_DPI

[getvictor]

There is a free browser based IDE for Verilog and SystemVerilog called EDA Playground. It is specifically designed for small prototypes and examples.

Currently, SystemVerilog support is limited to a few features, such as packages: http://www.edaplayground.com/s/4/26

EDA Playground is currently seeking a partner to offer limited public access for UVM simulations.

That said, UVM is fully supported for private deployments. Here is UVM code with sim results: http://www.edaplayground.com/s/4/64

[getvictor]

Update: EDA Playground now supports SystemVerilog and UVM. You can edit and simulate this simple UVM testbench: http://www.edaplayground.com/s/example/546

[sergeyb]

 

tried to compile but was not successfull

 

# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# -- Compiling package uvm_pkg
# ** Error: ./src/base/uvm_object_globals.svh(141): (vlog-2999) Enum literal 'UVM_DEEP' width (32) must match enum's witdth(28).
# 
# ** Error: ./src/base/uvm_object_globals.svh(142): (vlog-2999) Enum literal 'UVM_SHALLOW' width (32) must match enum's witdth(28).
# 
# ** Error: ./src/base/uvm_object_globals.svh(143): (vlog-2999) Enum literal 'UVM_REFERENCE' width (32) must match enum's witdth(28).

Thanks in advance

Sergei

[David Black]

Please show your code and describe where you are simulating. The error messages are interesting, but do not completely tell the story as error messages often show up pointing to the wrong code.

[sergeyb]

David, thank you for answering.

I have no any my code included. Just trying to compile UVM 1.2 (copied whole folder "src").

Tool is Modelsim Altera Starter 10.3d

 

Thanks , Sergei

 

vlog -work work -sv -stats=none  src/uvm_pkg.sv +incdir+./src
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# -- Compiling package uvm_pkg
# ** Error: ./src/base/uvm_object_globals.svh(141): (vlog-2999) Enum literal 'UVM_DEEP' width (32) must match enum's witdth(28).
# 
# ** Error: ./src/base/uvm_object_globals.svh(142): (vlog-2999) Enum literal 'UVM_SHALLOW' width (32) must match enum's witdth(28).
# 
# ** Error: ./src/base/uvm_object_globals.svh(143): (vlog-2999) Enum literal 'UVM_REFERENCE' width (32) must match enum's witdth(28).
# 
# ** Warning: ./src/seq/uvm_sequencer_base.svh(1381): (vlog-2186) SystemVerilog testbench feature
# 
# (randomization, coverage or assertion) detected in the design.
# 
# These features are only supported in Questasim.
# 
# ** Warning: ./src/reg/uvm_mem_mam.svh(701): (vlog-2186) SystemVerilog testbench feature
# 
# (randomization, coverage or assertion) detected in the design.
# 
# These features are only supported in Questasim.
# 
# ** Warning: ./src/seq/uvm_sequence_library.svh(766): (vlog-2186) SystemVerilog testbench feature
# 
# (randomization, coverage or assertion) detected in the design.
# 
# These features are only supported in Questasim.
# 
# c:/altera/15.0/modelsim_ase/win32aloem/vlog failed.

 

[prasadp4009]

Xilinx Vivado 2020.1 Supports UVM 1.2 and many features of Systemverliog. It supports the same in WebPack (Freeware) Version. I developed a tool "tbengy" to generate a UVM TB and Makefile. You can read the instructions on https://github.com/prasadp4009/tbengy

[David Black]

This appears to be a problem for Mentor Graphics since UVM-1.2 compiles fine with their other tools. It may be a limitation of ModelSim. As stated earlier, if you want to use UVM for learning/experimentation, then https://www.edaplayground.com is available. On the other hand, if you are wanting to do a real project, then you must purchase a full blown simulator from a commercial vendor.