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ljepson74

UVM_ACTIVE data type....bit or int ?

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When agents are configured, I typically see something like this:

uvm_config_db#(int)::set(this,"testbenchA.masterA_hostB.agentpink","is_active",UVM_ACTIVE);

 

 

Isn't UVM_ACTIVE of type bit?  I see it 'described' here in an enum and given a default value.

src/base/uvm_object_globals.svh: typedef enum bit { UVM_PASSIVE=0, UVM_ACTIVE=1 } uvm_active_passive_enum;

 

So shouldn't the uvm_config_db line not be:

 

 uvm_config_db#(int)::set(this,"testbenchA.masterA_hostB.agentpink","is_active",UVM_ACTIVE);

but instead be:

 uvm_config_db#(bit)::set(this,"testbenchA.masterA_hostB.agentpink","is_active",UVM_ACTIVE);

?
 
 
thx,
 
(I sense that I probably don't have a solid enough understanding of enum and the relationship between bits and ints.)

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Hello,

 

 

If you want to configure agent than you can do it in a following way.

 

 

 

//ethernet tx agent class declaration 
class eth_tx_agent extends uvm_agent;
  
uvm_active_passive_enum is_active=UVM_ACTIVE;//For active agent and if you want that agent will act as a passive than write UVM_PASSIVE instead of UVM_ACTIVE
 
  //macro registration
  `uvm_component_utils(eth_tx_agent)
 
//constuctor
function new(string name, uvm_component parent);
  super.new(name,parent);
endfunction:new
 
//agent subcomponent instatiation 
eth_driver dri;
eth_monitor mon;
eth_sequencer seq;
 
//build phase declaration-create agent's subcomponent
virtual function void build_phase(uvm_phase phase);
 
  super.build_phase(phase);
  mon=eth_monitor :: type_id::create("mon",this);
    if(is_active == UVM_ACTIVE)
begin
      seq=uvm_sequencer #(eth_transaction) ::type_id::create("seq",this);
dri=eth_driver :: type_id :: create("dri",this);
end
 
endfunction:build_phase
 
//connect phase declaration-connect component tlm port
virtual function void connect_phase(uvm_phase phase);
  if(is_active == UVM_ACTIVE)
begin
dri.seq_item_port.connect(seq.seq_item_export);
end
endfunction
 
endclass:eth_tx_agent
 
 
Regards,
Samrat

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Samrat,

 I don't see the connection between your response and my question.  Did you respond to the wrong topic, by chance?

 

 I did meander a bit with my question.  To clarify, what is the difference between the following two lines?

 uvm_config_db#(int)::set(this,"A.hostB","is_active",UVM_ACTIVE);

 uvm_config_db#(bit)::set(this,"A.hostB","is_active",UVM_ACTIVE);

 

Is the second one correct and the first one 'just works' (with Cadence irun v12.2) because of loose typing in systemverilog and/or my simulator?

(I see the second one in a fair number of 'examples' online.  This has been a minor hang-up and area of confusion for me as I attempt to improve my uvm_config_db understanding.) 

 

thx

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Hi,

 

The correct answer is the following:

uvm_config_db#(uvm_bitstream_t)::set(this, "A.hostB", "is_active", UVM_ACTIVE);

 

The code snippets in your post will not actually do anything (try setting "is_active" to UVM_PASSIVE with your code, it will have no effect).

If you look inside the uvm_agent base class, you will see the following:

 

virtual class uvm_agent extends uvm_component;

  uvm_active_passive_enum is_active = UVM_ACTIVE; // So the default setting for "is_active" is UVM_ACTIVE

  . . .

  function void build_phase (uvm_phase phase);

    int active;

    super.build_phase(phase);

    if (get_config_int("is_active", active)) is_active = uvm_active_passive_enum'(active);

  endfunction

  . . .

endclass

 

Since get_config_int is actually mapped to the method uvm_config_db#(uvm_bitstream_t)::get(cntxt,...) then the configuration setting must be of type uvm_bitstream_t. Inside the build_phase function, you can see that a static cast is used to convert to uvm_active_passive_enum.

 

Regards,

Steve

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