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mrforever

problem about variable part select in SystemVerilog

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Hi all,

I have one problem about variable part select of Verilog. If you know the width, but the upper or lower range is a variable, you can use variable part select.

eg : 

addr[idx_bits-:8] = {8{1'b1}}; 

t's okay.

 

But if you know the upper or lower range, the width is a variable, how can you do? I adapt the similar way of variable part select.

eg: 

addr[8-:idx_bits] = {idx_bits{1'b1}};

 

VCS reports such an error:

 

Error-[NCE] Non-constant expression  The following expression should be a constant.
  Expression: idx_bits
  Source info:     addr[8-:idx_bits] = {idx_bits{1'b1}};
 
Could anybody help to have a look? Thanks in advance.

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Hi,

 

Your problem is actually twice than you think - you must use a constant width both in the part select expression and in the replication expression:

addr[ const_or_var : const ] = { const { const_or_var } };

 

The trivial solution would be to loop through the target vector and assign its bits the value you need.

For example:

 

for (int i = 0; i < idx_bits; i++)
  addr[i] = 1'b1;

 

 

Of course, if you expect a wide part select and want to reduce the number of iterations, you may assign such a code:

int idx_bytes = idx_bits / 8;

for (int i = 0; i < idx_bytes; i++)
  addr[i*8 +: 8] = { 8 {1'b1} };

for (int i = idx_bytes * 8; i < idx_bits; i++)
  addr[i] = 1'b1;

 

 

Hope that helps.

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