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dakupoto

Strange VCD trace error with SystemC 2.2.0

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Could some SystemC guru please help ? My

questions are with respect to the source file

attached at the end.

Initially, INSTEAD OF ((vcd_trace_file*)fp)->sc_set_vcd_time_unit(1);

I had fp->sc_set_time_unit(1.0, sc_core::SC_NS);

Initially, I got the run time warning message:

SystemC 2.2.0 --- Aug 30 2011 19:39:07

Copyright © 1996-2006 by all Contributors

ALL RIGHTS RESERVED

Note: VCD trace timescale unit is set by user to 5.000000e-09 sec.

Trace Warning:

Multiple cycles found with same (2) time units count.

Waveform viewers will only show the states of the last one.

Use ((vcd_trace_file*)vcdfile)->sc_set_vcd_time_unit(int exponent10_seconds)

to increase time resolution.

SystemC: simulation stopped by user.

After the following change,

((vcd_trace_file*)fp)->sc_set_vcd_time_unit(4);

I got another runtime error message as:

SystemC 2.2.0 --- Aug 30 2011 19:39:07

Copyright © 1996-2006 by all Contributors

ALL RIGHTS RESERVED

Trace ERROR:

set_time_unit() has valid exponent range -15...+2.

WARNING: Default time step is used for VCD tracing.

SystemC: simulation stopped by user.

When I correct the time unit, and run it now, I do not

get either any compile or runtime error/warning message

but the VCD file, when viewed in GTKWave, shows up

as completely blank.

What could be the cause of this problem ? Is there a

problem with using 4 clocks together ? Any hints,

suggestions would be of immense help. Thanks in

advance.

#include "n2_cl_a1.h"

#include "syscsrcs.h"

#include "sysctrace.h"

#include "systemc.h"

#include <cstdlib>

#include <cstring>

int sc_main(int argc, char **argv)

{

sc_core::sc_signal<bool> sigin0;

sc_core::sc_signal<bool> sigin1;

sc_core::sc_signal<bool> sigin2;

sc_core::sc_signal<bool> sigin3;

sc_core::sc_signal<bool> sigout0;

sc_core::sc_signal<bool> sigout1;

sc_core::sc_clock master_clock("Clock",

10.0,

sc_core::SC_NS,

0.5);

sc_core::sc_clock si_sig("Si_Sig",

17.0,

sc_core::SC_NS, 0.65);

sc_core::sc_clock si_clk("Si_Clk",

23.0,

sc_core::SC_NS, 0.75);

sc_core::sc_clock so_clk("So_clk",

39.0,

sc_core::SC_NS, 0.85);

cl_a1_msffmin_fp_16x

cl_a1_msffmin_fp_16x_OBJ("cl_a1_msffmin_fp_16x");

syncdatasrc syncdatasrc_OBJ("syncdatasrc");

sc_trace_file *fp =

sc_create_vcd_trace_file("tr_cl_a1_msffmin_fp_16x");

((vcd_trace_file*)fp)->sc_set_vcd_time_unit(1);

syncdatasrc_OBJ.clk(master_clock);

syncdatasrc_OBJ.dout(sigin0);

cl_a1_msffmin_fp_16x_OBJ.d(sigin0);

cl_a1_msffmin_fp_16x_OBJ.l1clk(master_clock);

cl_a1_msffmin_fp_16x_OBJ.si(si_sig);

cl_a1_msffmin_fp_16x_OBJ.siclk(si_clk);

cl_a1_msffmin_fp_16x_OBJ.soclk(so_clk);

cl_a1_msffmin_fp_16x_OBJ.q(sigout0);

cl_a1_msffmin_fp_16x_OBJ.so(sigout1);

cl_a1_msffmin_fp_16x_OBJ.SCAN_MODE = false;

cl_a1_msffmin_fp_16x_OBJ.FAST_FLUSH = false;

sc_trace(fp, master_clock, "master_clock");

sc_trace(fp, sigin0, "data");

sc_trace(fp, si_sig, "si");

sc_trace(fp, si_clk, "siclk");

sc_trace(fp, so_clk, "soclk");

sc_trace(fp, sigout0, "q");

sc_trace(fp, sigout1, "so");

sc_core::sc_start(1000.0, sc_core::SC_NS);

sc_core::sc_stop();

sc_close_vcd_trace_file(fp);

return 0;

}

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Hello,

you should not use

((vcd_trace_file*)fp)->sc_set_vcd_time_unit(1);

to set the VCD time unit, as it is not part of IEEE Std 1666-2005 or later. Instead use sc_trace_file::set_time_unit() defined in IEEE Std 1666-2005 clause 8.1.2. You have to respect the constraint that the time unit has to be a power of ten. I suggest you to set it to the same value that you specify for the time resolution (clause 5.10.3), which also has to be a power of 10. I usually set it 1 ps or 1 fs (the latter in case of analog signals), as in my applications a high time resolution between events is important.

Regards, Torsten Maehne

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Hello,

In my original code, I had:

sc_trace_file *fp =

sc_create_vcd_trace_file("tr_cl_a1_msffmin_fp_16x");

fp->sc_trace_file::set_time_unit(1.0, sc_core::SC_NS);

In this case, I get the runtime warning as:

SystemC 2.2.0 --- Aug 30 2011 19:39:07

Copyright © 1996-2006 by all Contributors

ALL RIGHTS RESERVED

Note: VCD trace timescale unit is set by user to 1.000000e-09 sec.

Trace Warning:

Multiple cycles found with same (20) time units count.

Waveform viewers will only show the states of the last one.

Use ((vcd_trace_file*)vcdfile)->sc_set_vcd_time_unit(int exponent10_seconds)

to increase time resolution.

I have noticed that this warning is appearing now

only in those cases where there are more than one

clock in the test harness. For example, in this case

I have:

sc_core::sc_clock master_clock("Clock",

10.0,

sc_core::SC_NS,

0.5);

sc_core::sc_clock si_sig("Si_Sig",

17.0,

sc_core::SC_NS, 0.5);

sc_core::sc_clock si_clk("Si_Clk",

23.0,

sc_core::SC_NS, 0.5);

sc_core::sc_clock so_clk("So_clk",

39.0,

sc_core::SC_NS, 0.5);

I have a clock divider module, that is ied

the master clock, these issues do not appear

at all. Looks like somehow the VCD trace

generation module is getting confused by

these multiple clocks.

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