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How to handle single-cycle inter-thread depedencies?

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I hope this description makes sense. In the model I'm working on (which is a port of an existing model in SystemVerilog), there are two threads (rx and tx) that modify some shared flags. I am working on getting my timing as close to the SystemVerilog model as possible, and currently there is a problem of falling behind a few cycles because each cycle, the rx runs after the tx, where in the SV model the tx runs after the rx.


I believe that conceptually both threads are supposed to executing concurrently, so I know it may not make good sense to think of one thread executing before the other. So I am wondering what the best way to approach this is.


Is there a way to change the order in which threads sensitive to the same clock signal are executed? OR, do I need to concentrate on the shared data and communicate between threads with events?

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The SystemC scheduler is  co-operative (though there are now ways in SystemC 2.3.0 for one thread to kill another), i.e. one thread must suspend before another can run. The danger with shared variables is that your code is not deterministic - not only can thread execution order be different between SV and SystemC, it can be different between two implementations of SystemC (or two implementations of SV for that matter).


So if you require deterministic simulation with shared variables, you should control the order of execution of your threads explicitly, using e.g. events,




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