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sword_hs

What is the proper way to update the register model value when DUT update

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There are some status registes in the DUT, and the status registers' value in the DUT will update in the simluation.(e.g. some flags set). And how could the register model value be updated automatically? Is there someone could give me an example about the solution?

Thanks

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If you know when the status values are changing, and what the updated values are, you can update the reg model value by calling predict(). This updates the mirrored value in the model.

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Hi dwikle

Thanks for your response. Actually i don't know when the status values change. I just wanna monitor the DUT all the time, and if the status values changed, register model will update automatically.

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The only thing in the register API which could help you is uvm_reg::backdoor_watch(). However this is not implemented since there it's dependent on a simulator feature. The note from the documentation is:

User-defined DUT register change monitor

Watch the DUT register corresponding to this abstraction class instance for any change in value and return when a value-change occurs. This may be implemented a string-based DPI access if the simulation tool provide a value-change callback facility. Such a facility does not exists in the standard SystemVerilog DPI and thus no default implementation for this method can be provided.

The other options you have are to:

1) Create your own monitor on some internal DUT signal/register and call predict() when it changes.

2) Simply don't check the register value on reads. This may be desired for status fields that you're not fully modeling, or fields that return non-deterministic values on reads such as counters.

For option (2) you need to call field.set_compare(UVM_NO_CHECK) after the field has been created and configured.

-Doug

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Hi Doug

Thanks for your more detailed solution about my question. The two options you mentioned are very useful. And the first solution you mentioned that used uvm_reg::backdoor_watch(). what you means is that it will depend on the simluation tool's feature, right? And I found a solution in the uvm_user_guide_1.1:

class active_monitor_r1 extends uvm_reg_backdoor;

virtual function bit is_auto_updated(string fld_name);

case (fld_name)

"f1": return 1;

"f2": return 1;

endcase

endfunction

virtual task wait_for_change();

@($root.tb_top.dut.rf.f1 or $root.tb_top.dut.rf.f2);

endtask

endclass

I just tried to figure out it in this way. but the simulation is error , info as "illegal location for a hierarchical name (in a package)."

So have you met this? Could you help me about this.

Thanks so much for your help.

Edited by sword_hs

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You have to implement Active Monitoring.  This is described in the User's Guide 5.6.6

 

Essentially you need to implement the wait_for_change.  The problem with this is it takes hard-coded paths - not a string, which is how we reference registers and fields in the register model.

 

I've implemented this with a fork/join and hard paths -- which really isn't that re-usable.

 

There are free packages like the one from Verilab that has this implementation.  It has a nice white paper and presentation.  You need to support C-DPI in your simulator.  The code involves both a SV and C-DPI.  It is an Apache license, so you need to honor it.

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You have to implement Active Monitoring.  This is described in the User's Guide 5.6.6

 

Essentially you need to implement the wait_for_change.  The problem with this is it takes hard-coded paths - not a string, which is how we reference registers and fields in the register model.

 

I've implemented this with a fork/join and hard paths -- which really isn't that re-usable.

 

There are free packages like the one from Verilab that has this implementation.  It has a nice white paper and presentation.  You need to support C-DPI in your simulator.  The code involves both a SV and C-DPI.  It is an Apache license, so you need to honor it.

 

Hi lkb1963,

   Thanks so much for your response. You mean that you have implemented this with a fork/join, so could you paste some code example? Actually, I have tried implemented the active monitoring, and because of the package reason, there should not be hard paths used in the active monitoring. Could you give me more detailed explanation. And could you tell me the white paper title to search?

Thanks in advanced.

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Sorry for the late response,

 

I don't seem to be getting emails from this site.  Even though I signed up.

 

Go to:http://www.verilab.com/resources/papers-and-presentations/

 

There is a good presentation and paper and code a page down:

 

SNUG Europe 2012: I Spy with My VPI - Monitoring signals by name, for the UVM register package and more

Lisa

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