santhosh Posted March 15, 2013 Report Share Posted March 15, 2013 hi i am new to UVM. In my design i have in-out port so interface i declared as wire. while run the design by using make i got the one error : ** Error: (vsim-3044) ../uvc/i2c_slave_driver.sv(55): Usage of 'vif.sda' inconsistent with 'net' object. here sda is in-out singal and vif is virtual interface of the design. can any one help me to solve this problem.. Regards, Santhosh Quote Link to comment Share on other sites More sharing options...
dave_59 Posted March 15, 2013 Report Share Posted March 15, 2013 I'll bet you are trying to make a procedural assignment to a wire. That is illegal. See my DVCon paper "The Missing Link: The Testbench to DUT Connection" about handling bidirectional signals in a testbench. Quote Link to comment Share on other sites More sharing options...
santhosh Posted March 18, 2013 Author Report Share Posted March 18, 2013 Thank you dave_59. For your valuable pdf. its nice.. Quote Link to comment Share on other sites More sharing options...
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