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Error-[SE] Syntax error

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In my env I am using vcs2012.09-Beta3 and uvm1.1b-0. I got following compilation error.

Error-[sE] Syntax error

Following verilog source has syntax error :

"/tool/pandora64/.package/uvmkit-1.1b-0/uvm/src/tlm1/uvm_sqr_ifs.svh", 37:

token is 'uvm_object'

virtual class uvm_sqr_if_base #(type T1=uvm_object, T2=T1);

Thanks in advance

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Please do not use Beta Software.

VCS2012.09-3 is the latest version and you should switch to it immediately.

First ensure your testbench works by using vcs "-ntb_opts uvm " switches, then you can enable your own or UVM-1.1b version by using setenv VCS_UVM_HOME /tool/pandora64/.package/uvmkit-1.1b-0/uvm/src

If you still see an issue then email the compilation logfile to vcs_support@synopsys.com


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