mrforever Posted December 26, 2012 Report Share Posted December 26, 2012 Hi, all experts i met one runtime error as follow. The option "+UVM_PHASE_TRACE" added is used to trance the uvm_phase. It seems like being stuck in some uvm_phase and then generates the vcs runtime internal error? Could anybody give me some clue? Thanks in advance. Command: ./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log Chronologic VCS simulator copyright 1991-2012 Contains Synopsys proprietary information. Compiler version G-2012.09; Runtime version G-2012.09; Dec 26 12:19 2012 ---------------------------------------------------------------- UVM-1.1c © 2007-2012 Mentor Graphics Corporation © 2007-2012 Cadence Design Systems, Inc. © 2006-2012 Synopsys, Inc. © 2011-2012 Cypress Semiconductor Corp. ---------------------------------------------------------------- *********** IMPORTANT RELEASE NOTES ************ You are using a version of the UVM library that has been compiled with `UVM_NO_DEPRECATED undefined. See http://www.eda.org/svdb/view.php?id=3313 for more details. (Specify +UVM_NO_RELNOTES to turn off this notice) UVM_INFO @ 0: reporter [RNTST] Running test test_config... UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common' (id=55) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common' (id=55) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.build' (id=73) Scheduled from phase common UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.build' (id=73) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.build' (id=73) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.connect' (id=85) Scheduled from phase common.build UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.connect' (id=85) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.connect' (id=85) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.end_of_elaboration' (id=97) Scheduled from phase common.connect UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.end_of_elaboration' (id=97) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.end_of_elaboration' (id=97) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.start_of_simulation' (id=109) Scheduled from phase common.end_of_elaboration UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.start_of_simulation' (id=109) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1381) @ 0: reporter [PH/TRC/DONE] Phase 'common.start_of_simulation' (id=109) Completed phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'common.run' (id=121) Scheduled from phase common.start_of_simulation UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1403) @ 0: reporter [PH/TRC/SCHEDULED] Phase 'uvm' (id=170) Scheduled from phase common.start_of_simulation UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'common.run' (id=121) Starting phase UVM_INFO /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_phase.svh(1124) @ 0: reporter [PH/TRC/STRT] Phase 'uvm' (id=170) Starting phase Command line: ./simv./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log Command line: ./simv +UVM_VERBOSITY=UVM_LOW +UVM_TESTNAME=test_config +UVM_PHASE_TRACE -l run.log --- Stack trace follows: No context available VCS runtime internal error (core dumped) . Please contact vcs_support@synopsys.com or call 1-800-VERILO Quote Link to comment Share on other sites More sharing options...
mrforever Posted December 26, 2012 Author Report Share Posted December 26, 2012 stuck at starting_phase? Quote Link to comment Share on other sites More sharing options...
adielkhan Posted January 2, 2013 Report Share Posted January 2, 2013 VCS should not error out like that, please send the testcase to vcs_support@synopsys.com thanks adiel. Quote Link to comment Share on other sites More sharing options...
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