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Showing results for tags 'verilog'.
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am91 posted a topic in IP-XACT DiscussionHi, I am using the IPXACT 2009 standard to describe a verilog module. The module has a bunch of parameters and ports whose width depends on these parameters. I had a couple of questions regarding this: 1) Do the parameters go under "<spirit:model>..<spirit:modelParameters>" or under ""<spirit:model><spirit:views><spirit:view><spirit:parameters>" ? 2) From what I understand, there seems to be way to describe variable width ports in the 2014 standard but not in the 2009 standard? Thanks.
cliffc posted a topic in UVM Simulator Specific IssuesUsing VCS, I can compile and run multiple top-level modules. In the example I am running, I have a dut module and a bind-file module. The bind-file module is nothing more than: module bindfiles; bind dut pLib_dut p1 (.*); endmodule When I compile and run, I indeed see both top modules have been compiled: Top Level Modules: bindfiles dut And both run just fine as expected. Now the question: If I compile both top modules, can I run simv with just the dut module and ignore the bindfiles module? I would like to simulate both with the bindfiles and without the bindfiles module if possible without re-ocmpiling. Thanks - Cliff Cummings Sunburst Design, Inc.