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Showing results for tags 'uvm_sequence'.
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firstname.lastname@example.org posted a topic in Methodology and BCL ForumHi there We want to traverse through all registers present in a UVM_REG_BLOCK based on increasing address. We have the following pseudocode: model.NTB_DB.get_registers(total_regs_ntb); foreach (total_regs_ntb) begin total_regs_btb.write(status, wdata, .parent(this)); end But, the above source code does not go through the registers space based on address. ie., When I have a 2-dimensional array of registers, array indices are chosen first(not addresses). Any help to workaround this problem is appreciated. Best regards Balasubramanian G
mrforever posted a topic in Methodology and BCL ForumHi all, How to pass the value to the variable of uvm_sequence object? 1. use uvm_config_db 2. assign directly When i use the first way, i found that maybe uvm_config_db::get() can only use in the uvm_component class. Then i use the second way, I cann't pass the value to the variable successfully. Does anybody know the reason? Thanks in advance. pieces of code of the first way: In top: uvm_config_db#(uvm_bitstream_t)::set(uvm_root::get(), "*", "my_cpu_id", HOST_NUM); In my_sub_sequence which extends from uvm_sequence: void'(uvm_config_db#(uvm_bitstream_t)::get(this, "", "my_cpu_id", my_cpu_id)); Result: VCS reports error. pieces of code of the second way: In v_sequence: for (int i = 0; i < host_num; i++) begin inst_name = $sformatf("sub_seq[%0d]", i); //sub_seq[i] = my_sub_sequence::type_id::create(inst_name,,get_full_name()); sub_seq[i] = new(inst_name); sub_seq[i].my_cpu_id = i; end In my_sub_sequence: int my_cpu_id; ... virtual task body(); ... $display("my_cpu_id = %0d", my_cpu_id); ... endtask Result: every my_cpu_id's value display 0, not 0, 1, 2, 3.