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Showing results for tags 'uvm_reg_field'.
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timothy posted a topic in Methodology and BCL ForumIn my test sequence, some fields of a register are changed frequently and others are keep previous value. I wrote the code like below, register.fieldY.set(value) register.update(status) // first update ... other code regsiter.fieldY.set(new_value) register.update(status) // second update The first update was processed but the second update was not seen in the system bus. I digged into UVM manual and implementation, and found out that 'update' function doesn't update mirrored value. By change, new_value was same to reset value of fieldY. So at that time the second update was called, m_mirrored and m_desired were same. That was the reason of no bus transaction. I tried below codes, and they updated my register properly. register.fieldY.set(value) register.write(register.get(), status) register.fieldY.set(value) register.update(status) register.predict(register.get(), status) However, they look like strange for me. Why I need to set desired value explicit by getting their internal desired value? Are my solutions wrong? Are there better ways in this case?
Hi, I wanted to use the field.mirror() task provided in the uvm_reg_field class to check only a particular field. However, I see that the field.mirror() task is just calling the parent register mirror task. Hence the entire register is read and compared which I didn't intend to do. I tried this in my sequence and I see the above mentioned behavior. This looks like a serious bug. Can you please confirm this. Regards, Shreyas