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Showing results for tags 'uvm_monitor'.
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is it common not to have uvm_monitor without parameter? For example, the following is a snippet from uvm reference guide. The monitor does not have any parameter while driver has user defined sequence_item as a parameter class master_monitor extends uvm_monitor; virtual bus_if xmi; // SystemVerilog virtual interface bit checks_enable = 1; // Control checking in monitor and interface. bit coverage_enable = 1; // Control coverage in monitor and interface. class simple_driver extends uvm_driver #(simple_item); simple_item s_item; virtual dut_if vif; // UVM automation macros for general components `uvm_component_utils(simple_driver Does this mean that I cannot have multiple instances of monitor with different sequence_item types as class is not type parameterized?
cliffc posted a topic in UVM (Pre-IEEE) Methodology and BCL ForumThe parameterized uvm_driver base class includes a built-in uvm_seq_item_pull_port called seq_item_port. The parameterized uvm_sequencer base class includes a built-in uvm_seq_item_pull_imp called seq_item_export. These are always connected in the agent. Every UVM agent that I create has a tb_monitor extended from the uvm_monitor and everyone declares a uvm_analysis_port. Question for UVM Library Developers: Is there any reason the uvm_monitor base class should not be enhanced to be parameterized to the transaction type and include a built-in uvm_analysis_port? Regards - Cliff Cummings