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Found 3 results

  1. Hi, I am seeing member reference resolution error related to uvm_analysis_imp_decl. Linenum52:`uvm_analysis_imp_decl(_mon).Please see in below code. You can see the error as well below which got during elaboration. I tried to connect monitor analysis port to another component analysis export. Giving quick solution is help for me. // Code your testbench here // or browse Examples // Code your testbench here // or browse Examples // Code your testbench here // or browse Examples class transaction #(parameter LENGTH=10) extends uvm_sequence_item; rand bit a; `uvm_object_param_utils_begin(transaction#(LENGTH)) `uvm_field_int(a,UVM_ALL_ON) `uvm_object_utils_end function new(string name="transaction"); super.new(name); endfunction endclass class monitor#(parameter LENGTH=5) extends uvm_monitor#(transaction#(LENGTH)); `uvm_component_param_utils(monitor#(LENGTH)) transaction#(LENGTH) tr; uvm_analysis_port#(transaction#(LENGTH)) analysis_port; function new(string name="monitor",uvm_component parent); super.new(name,parent); endfunction task run_phase(uvm_phase phase); tr=new("mahen"); $display("mahen"); analysis_port.write(tr); endtask endclass Linenum52:`uvm_analysis_imp_decl(_mon) class model#(parameter LENGTH=5) extends uvm_component#(transaction#(LENGTH)); `uvm_component_param_utils(model#(LENGTH)) uvm_analysis_imp_mon#(transaction#(LENGTH)) mon_export; transaction#(LENGTH) tr; function new(string name,uvm_component parent); super.new(name,parent); mon_export=new("mon_export",this); endfunction function write_mon(transaction#(LENGTH) trans); $display("in_monitor"); endfunction endclass class env#(parameter LENGTH=5) extends uvm_component#(transaction#(LENGTH)); `uvm_component_param_utils(env#(LENGTH)) model#(LENGTH) md; monitor#(LENGTH) mon; function new(string name,uvm_component parent); super.new(name,parent); endfunction function build_phase(uvm_phase phase); super.build_phase(phase); md=model#(LENGTH)::type_id::create("model",this); mon=monitor#(LENGTH)::type_id::create("mon",this); endfunction function connect_phase(uvm_phase phase); mon.analysis_port.connect(md.mon_export); endfunction endclass class test#(parameter LENGTH=5) extends uvm_component#(transaction#(LENGTH)); //`uvm_component_param_utils(test#(LENGTH)) typedef uvm_component_registry#(test#(LENGTH),"test") type_id ; env#(LENGTH) en; function new(string name,uvm_component parent); super.new(name,parent); endfunction function build_phase(uvm_phase phase); super.build_phase(phase); en=env#(LENGTH)::type_id::create("env",this); endfunction task run_phase(uvm_phase phase); #10; endtask endclass module top; parameter LENGTH=10; typedef test#(LENGTH) delay_test; initial run_test(); endmodule Parsing design file 'design.sv' Parsing design file 'testbench.sv' Top Level Modules: top Warning-[TMPO] Too many parameter overrides testbench.sv, 31 The extra parameter overrides will be ignored. Source info: uvm_monitor#(transaction#(LENGTH) ) Warning-[TMPO] Too many parameter overrides testbench.sv, 53 The extra parameter overrides will be ignored. Source info: uvm_component#(transaction#(LENGTH) ) Warning-[TMPO] Too many parameter overrides testbench.sv, 76 The extra parameter overrides will be ignored. Source info: uvm_component#(transaction#(LENGTH) ) Warning-[TMPO] Too many parameter overrides testbench.sv, 105 The extra parameter overrides will be ignored. Source info: uvm_component#(transaction#(LENGTH) ) TimeScale is 1 ns / 1 ns Error-[MRRE] Member reference resolution error testbench.sv, 52 Member operator "." cannot be used on object of type int. Expression: m_imp Source info: m_imp.write_mon 4 warnings 1 error CPU time: 3.017 seconds to compile Exit code expected: 0, received Thanks, Preneeth
  2. In my earlier UVM days I ran into this confusing error message a number of times. I just hit it again, so am posting my solution here, to share and to help myself rediscover when it is time. Error (running IUS 13.1): uvm_analysis_imp_my_snoop #( xyz_trans, my_scoreboard) my_snoop_port; | ncvlog: *E,EXPENC (/user/goblin_dev/tb/my_scoreboard.svh,60|50): Expecting the keyword 'endclass'. Below is the pseudo code w/o the error. In converting the real code to pseudo code (to make it more succinct and sterilized), I do not believe I created any inconsistencies, but this is not what was compiled, of course. `uvm_analysis_imp_decl(_my_snoop) class my_scoreboard extends uvm_scoreboard; `uvm_component_utils(my_scoreboard) uvm_analysis_imp_my_snoop #( xyz_trans, my_scoreboard) my_snoop_port; function void build_phase(uvm_phase phase) my_snoop_port = new("my_snoop_port",this); endfunction : build_phase function void write_my_snoop( xyz_trans t ); //guts here endfunction : write_my_snoop endclass : my_scoreboard The error occurred when the following line was missing from above. `uvm_analysis_imp_decl(_my_snoop) So, without this macro called, the uvm_analysis_imp_my_snoop class is not declared. So, I would think that the error message would instead say that the class was not found. (I should try removing some random class that my tb needs and see what error message appears - b/c that is the error message I would expect here as well.) Appendix: The following code is taken from uvm-1.1/uvm_lib/uvm_sv/src/macros/uvm_tlm_defines.svh : // MACRO: `uvm_analysis_imp_decl // //| `uvm_analysis_imp_decl(SFX) // // Define the class uvm_analysis_impSFX for providing an analysis // implementation. ~SFX~ is the suffix for the new class type. The analysis // implemenation is the write function. The `uvm_analysis_imp_decl allows // for a scoreboard (or other analysis component) to support input from many // places. For example: // //| `uvm_analysis_imp_decl(_ingress) //| `uvm_analysis_imp_decl(_egress) //| //| class myscoreboard extends uvm_component; //| uvm_analysis_imp_ingress#(mydata, myscoreboard) ingress; //| uvm_analysis_imp_egress#(mydata, myscoreboard) egress; //| mydata ingress_list[$]; //| ... //| //| function new(string name, uvm_component parent); //| super.new(name,parent); //| ingress = new("ingress", this); //| egress = new("egress", this); //| endfunction //| //| function void write_ingress(mydata t); //| ingress_list.push_back(t); //| endfunction //| //| function void write_egress(mydata t); //| find_match_in_ingress_list(t); //| endfunction //| //| function void find_match_in_ingress_list(mydata t); //| //implement scoreboarding for this particular dut //| ... //| endfunction //| endclass `define uvm_analysis_imp_decl(SFX) \ class uvm_analysis_imp``SFX #(type T=int, type IMP=int) \ extends uvm_port_base #(uvm_tlm_if_base #(T,T)); \ `UVM_IMP_COMMON(`UVM_TLM_ANALYSIS_MASK,`"uvm_analysis_imp``SFX`",IMP) \ function void write( input T t); \ m_imp.write``SFX( t); \ endfunction \ \ endclass
  3. Below I define a uvm_scoreboard. Why will this not compile when I remove the (3) lines THIS AND THAT? Should it? `uvm_analysis_imp_decl(_rcvd_pkt) //THIS class dpx_rr_scoreboard extends uvm_scoreboard; `uvm_component_utils(dpx_rr_scoreboard) virtual function void write_rcvd_pkt(input some_trans t); //AND THAT endfunction : write_rcvd_pkt //AND THAT endclass : dpx_rr_scoreboard I am using irun 12.X and get the following error when I remove the aforementioned lines: class dpx_rr_scoreboard extends uvm_scoreboard; | ncvlog: *E,FAABP1 (/user/posedgeclk/tb/dpx_rr_scoreboard.svh,25|46): task, function, or assertion instance does not specify all required formal arguments [10.2.2][10\ .3(IEEE)]. I poked around in the uvm class library just a bit, but did not figure this out. Any ideas? Is this a uvm thing or Cadence thing (trying to enforce that I write sensible code) or just fooling thing on my part? I am asking Cadence directly as well, but wanted to throw this out to the crowd. **I am just trying to get a shell of a scoreboard compiling, and don't care that it doesn't do anything yet. Let's ignore the fact that I don't have uvm_analysis_imp_rcvd_pkt created.
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