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Found 63 results

  1. The VCS implementation of uvm_reg_bit_bash_seq UVM register bit bash sequence performs a model.reset() in the sequence body, before starting the core do_block() task. Due to this reset, any configurations made to the DUT before starting the bit bash sequence is lost in the mirror model, while the DUT still has the configuration intact. This is causing failures during the bit-bash process, resulting in a test fail. There is no knob to override the reset functionality, nor can I extend the sequence and bypass the reset. Any thoughts on this? Any work around for this? ~Chethan
  2. I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!
  3. The cook book from Mentor tells following and in another thread, the moderator also suggested against using the sub phases of run. However in one of my projects, I do find the need for using them (and infact we had an internal implemention of something similar in our previous OVM version). Are there any thing happening on this front? Is there a risk in using the sub phases if some of that changes in a future version? "The Accellera UVM committee is still developing the use models and APIs for new UVM phasing as it relates to sequences and transactors. In the mean time, our recommendation is to wait until that work is done and the API is stable. There are a number of future articles in this section which will be available here at that time, and which will describe our recommendations for using this technology. These include: How to make your testbench phase aware [Not yet available] How to manage sequences in the context of phasing [Not yet available] How to design reusable transactors that work in the context of phasing [Not yet available] "
  4. Let's say I have the following DUT. The UVM environment contains a chain of models/predictors. Input data flows down this chain and generates the expected CHIP output, which is compared to actual. Pros: verifies top-level functionality. Cons: Does not verify block level functionality. A good start, but I'd like to also verify the blocks in a system setting. So, I create block-level environments, then reuse them at the top level. Awesome, but wait a minute. I still need the top-level verification (Input-to-Output) like in the first example. However, all 3 of my block predictors are being used in their corresponding environments' scoreboards, hooked up to the RTL, via agents. How does one do both? Surely I'm not supposed to instantiate duplicate copies of my block level predictors to create the end-to-end model chain...
  5. Hi, We are using snps ralgen to generate the regmodel. It appears that the ralgen creates only the default map. We would like to have 2 maps for 2 separated if masters. Is there an online example for such case? A post gen script can do one of the following 2 options: 1. add another instance of uvm_reg_map and copy/clone the ready map after finished build 2. add another instance of uvm_reg_map, and duplicate any map1.add_reg and map1.add_submap to map2 Which is preferable? Thanks! Elihai
  6. I see uvm_sequencer_base::wait_for_grant (UVM 1.1d) is a virtual task but accesses a local int g_request_id - is this not a bad coding style? If I were to override this virtual method for debug with much of the code intact tool throws an error for his local bar in a derived SQR class. I extended a SQR class and copied all the code for wait_for_grant and started tweaking - couldn't proceed with that debug due to this member being local. Should it be protected instead of local? Thanks Srini
  7. Is it possible to do a uvm_config_db::set() for an object of derived class type using the base class handle and later do a uvm_config_db::get() of same object using the derived class handle Since a base class handle can be used to point to a derived class object and later typecase, I thought this would work, but doesn't seem to be so. Any help will be appreciated? Here is an example class BaseA ; endclass class DerivedA extends BaseA endclass 1) Set config_db DerivedA a1; a1 = DerivedA::create() uvm_config_db#(DerivedA)::set(this, "" , "myobj", a1); 2) Get config_db BaseA a1; DerivedA a2; uvm_config_db#(BaseA)::get(this, "" , "myobj", a1); $cast(a2, a1);
  8. I need to have two uvm_tlm_target_socket in a class and I need to do different set of things with the data received via two sockets. I was thinking if it is possible to have two implementation of b_transport task. I am aware of how we can have multiple analysis port imp and use uvm_analysis_imp_decl(_something) and we can have a "write_something" implementation. Is something similar available for uvm_tlm_target_socket? Regards, Gautam
  9. Hi, I notice something interesting in the build_phase order of uvm_component. The uvm_component at the same level are build in the alphabetatical order of the instance name. I expect the build order would be the same as the order I call the factory create function. I am wondering is the alphabetatical build order an intended feature of UVM or just some artifact of the implementation? I couldn't find any reference to this behavior in the UVM user guide or the class reference library. Thanks. Horace
  10. I'm trying to run uvm-systemc on macosx. Link to download: In the install flow, ../configure works fine, but on make i get this error: Making all in macros CCLD libmacros.laar: no archive members specifiedusage: ar -d [-TLsv] archive file ... ar -m [-TLsv] archive file ... ar -m [-abiTLsv] position archive file ... ar -p [-TLsv] archive [file ...] ar -q [-cTLsv] archive file ... ar -r [-cuTLsv] archive file ... ar -r [-abciuTLsv] position archive file ... ar -t [-TLsv] archive [file ...] ar -x [-ouTLsv] archive [file ...]make[4]: *** [] Error 1make[3]: *** [all-recursive] Error 1make[2]: *** [all-recursive] Error 1make[1]: *** [all] Error 2make: *** [all-recursive] Error 1 I've looked online, and it seems that it is a makefile problem. However the uvm-systemc makefile is way to complex for me to comprehend where the issue could reside. Any ideas on why is this happening? Thanks
  11. In case of UVM ,config_db can be accessed in any component or object which helps mainly the dynamic creation of component/models.Whether any option is present in SYSTEM C ?
  12. Hi, I have a doubt about requirement of raise/drop_objection. Why does a compiler need objections in run_phase? Why can it not just wait for time given like 100ns as following example? Ex. task run_phase(uvm_phase phase); //phase.raise_objection(this); #100ns; //phase.drop_objection(this); endtask
  13. Hi all, I'm new with UVM and I came across a problem. I am working on an AXI RD VIP using UVM and I have the following issue. In the data_phase (the data channel driving) from the MASTER driver, I need to drive the RREADY signal. There are 3 handshake types described in the protocol specifications: valid before ready, ready before valid and ready and valid at the same time. In case of valid before ready, I want to wait a certain number of clock cycles ( delay ) from the time that RVALID asserted and then to assert the RREADY signal. From my understanding, all the delay information should come from the transaction(sequence_item). The problem is that I generate a new transaction (sequence_item) with get_next_item only when I drive the address channel (in address_phase); The data_phase works in parallel with the addr_phase and its independent of the address phase. Also the data_phase needs multiple delay values (one for each data received from DUT, ex. arlen+1) while I only generate one transaction that contains the address channel informations. Code example: task run_phase(uvm_phase phase) fork forever begin ... seq_item_port.get_next_item(req); address_phase(req); seq_item_port.item_done(); end forever begin data_phase(); end endtask : run_phase task address_phase(axi_item item); // Drive the address channel ... endtask : address_phase task data_phase(); // Wait for the rvalid signal while(!vif.rvalid) @(posedge vif.clk); // Insert delay between rvalid assertion and rready assertion repeat(<problem!!!!>) @(posedge vif.clk); rready = 1; ... endtask : data_phase I don't know what variable (sequence_item variable) to set in the <problem!!!> Can anyone give me an advice regarding this problem. I repeat, I want all timing related data to be set from the sequence_item Regards, Adrian
  14. Hello there, As per Mentor's UVM guidelines 5.2 [1], reset_phase() will be obsolete in future releases. During DVCon 2014, Cadence recommends to use run_phases() on slide 5 of [2]. With the release of UVM-1.2, I believed that the sub-phases of run_phase are now stable and clean. Now with the recommendations above, it seems that the it's better to stick with run_phase() itself. As UVM delelopers, what are your views about it ? What do you recommend ? My intention is not to start a flame war of any kind. But to understand which route to opt in order that most of my UVM code would be compatible with UVM 1.3. All in all, it appears that there is a miscommunication on the web. [1]: [2]: regards, Chitlesh
  15. Hi All, I have a sequence sending a created and randomized item using `uvm_send. The driver receives an item using try_next_item. Upon receiving, it drives the item and calls item_done. Using debug message after item_done, I can clearly see that item_done is called and returned but `uvm_send in sequence is still blocked and not doing forward to send next item (it implements a loop). Can anyone help me with possible reasons why `uvm_send would not return even when driver has called item_done and come out of item_done. Thanks in advance! Ninad
  16. Hi all, I'm doing verification for an PHY between SPI master and a memory chip. I make two agents one for master to transfer the request, one mimics the memory slave to reply. PHY will be hooked up to two interfaces that of SPI Master and Memory. During sending request and reply data, Chip Select Pin (in SPI interface) must go low to enable the transaction. But I don't know how to control this pin when It sends the reply from memory. Because this pin is not an interface of memory slave agent. Could anyone give me some advice? Could I use phases to control the env that has different agents? Thank you, Nhat
  17. Hello, I'm trying to implement an AXI Slave VIP and have few questions regarding the implementation. In this case, the DUT is the master. The AXI Slave checks the interface for valid read /write signals and performs a read/write operation from a memory model. It returns back the write response/read data back to the DUT. 1. Since this is a slave VIP , do I need a slave sequence which runs forever sending transactions to the driver ? This is similar to the UVM example where the monitor and sequencer are connected by an analysis port and the sequence calls the peek function to check if a valid transaction is available from the monitor. (OR) 2. Can I skip the sequence/sequencer part and just connect my monitor and driver using an analysis port and pass on the observed transaction from the monitor to the driver for further action ? (OR) 3. Im thinking of a 3rd alternative of just using the monitor to the observe the interface and drive back the write response/ read data back using the monitor itself and leave the driver empty. Please let me know your valuable thoughts and suggestions. Thanks, Madhu
  18. Hi, As per my understanding, connect_phase does not start until all build_phase do not complete. How is this mechanism controlled? I did not find anything in uvm reference manual about this. Please let me know if there is any. Thanks.
  19. The Easier UVM Coding Guidelines

    Version 2016-06-24


    This document is a printable version of the Easier UVM Coding Guidelines from Doulos. You are free to use these guidelines directly, to merge them into your own company-specific UVM coding guidelines, or merely to borrow some of the ideas. These coding guidelines are offered by Doulos for the benefit of the UVM community. They are not officially endorsed by Accellera.
  20. Hi all I'm trying to build a generlc verification environment for specific modules of mine, that essentially only differ (besides their actual implementation) by the number of inputs/outputs of a certain interface standard and the data_size of each of these interfaces. This leads to the point, that I like to have an environment, where I can set the number of interfaces and for each of these interfaces the data_size. Unfortunately this simple setup of non-dynamic pre-compile settings is getting me in a lot of trouble. (1) Sequence_Item class input_item #(int unsigned data_size) extends uvm_sequence_item; `uvm_object_param_utils(input_item) rand logic[data_size-1:0] data; ....... The first question that comes to mind writing this code is the following: Is it possible to factory overwrite a param. class with another specilisation of that same class (e.g. define a driver with input_item<32> and then factory overwrite it with input_item<42>)? Otherwise a item_base class would be necessary that than would be extended by this class. (2) Analysis Ports class env extends uvm_env; .... // need N = number of interfaces analysis ports between each monitor and scoreboard uvm_analysis_port #(input_item#(17)) ap_1; uvm_analysis_port #(input_item#(12)) ap_2; ..... uvm_analysis_port #(input_item#(42)) ap_N; .... Due to the different input_items all ports are of a different type. Therefore it is not possible to create an array of N=number_of_interfaces, which leads to this not being possible to implement. Furthermore the analysis_port/export classes cannot be overwritten through the means of the factory. (3) Virtual Sequence class top_vseq_base extends uvm_sequence #(uvm_sequence_item); `uvm_object_utils(top_vseq_base) uvm_sequencer #(input_item#(17)) seq_1; uvm_sequencer #(input_item#(12)) seq_2; ... uvm_sequencer #(input_item#(42)) seq_N; In the virtual sequence I essentially run into two problems: 1. The first one is the same problem as in (2) of not being able to create an array of different types or having a pre-processor for-loop 2. The other one is the fact, that I'm not able to get access to the number N . Even if they were all of the same type and I would declare a dynamic array, there is no build_phase and no way to get informations through either the config_db or "p_sequencer.variable". I could put a member variable into the virtual sequencer, but I'm not sure if it is a good idea/possible to create a dynamic array in the body method. General Solutions so far: I only see two solutions here ... 1. Defining a gigantic input_item with data_size of 256/512 and then cut it everywhere. But unfortunately I will be in need of an array of completely different items in the next version of this environment anyhow. The reason for that is, that I would like to group a bunch of M different interfaces into one environment, all of them running a different item. Therefore the analysis_ports would all run a different item. 2. Just building a code generator, in which the user sets all parameters, creating the necessary environment for the given DUT. If you have any input, I would be glad to hear it. Thanks Marcel
  21. UVM-ML Open Architecture

    Version version 1.6


    UVM-ML Open Architecture - version 1.6 Enabling Multi-Language and Multi-Framework Verification March, 2016 General Overview Universal Verification Methodology Multi-Language (UVM-ML) provides a modular solution for integrating verification components written in different languages into a unified and coordinated verification environment. It consists of an open source library that enables such integrations, and can be extended to support additional languages and methodologies. This release of the UVM-ML implementation is the result of collaboration work between Advance Micro Devices, Inc., and Cadence Design Systems, Inc. It expands on the mature technology provided by Cadence in Incisive and in previous UVM-ML postings on UVMWorld. It is provided as open source under the Apache 2.0 license. This distribution includes the following main elements Backplane implementation and API Example frameworks and adapters (three provided: UVM-SV, UVM-e, and UVM-SC) Several demos and high level examples (showing all frameworks interacting) and a few smaller feature examples (tests) Docs directory with a Reference manual, User Guide and reference HTML docs Information on all news and features can be found in the ml/docs/ directory. This UVM-ML package is intended to serve as a basis for the verification community to collaboratively expand and evolve the multi-language verification methodology. Please read the “Status, Use, and Disclaimers” section below for full details. Where to Find Information Where to start reading: point your web browser to ml/README.html The landing page provides links to installation directions, release notes, user guide, and more. For feedback or questions: send email to An easy installation and Setup video guide is available You can checkout the update of David I. Long form Doulos at DVCon 2016 in the US. It relates to UVM-ML (along with other updates). Blog series: Multi-Language Verification Environment—Getting First Run in Few Minutes Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using UVM ML Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi-Language Environment Multi-Language Verification Environment (#4)—Multi-Language Hierarchy Debugging Multi-Language Verification Environments Platforms and Simulators This release of UVM-ML should run on any simulator supporting one or more of the standard languages: IEEE 1800 (SystemVerilog), IEEE 1647 (e), and IEEE 1666 (SystemC). It was tested on the Linux operating system with various combinations of simulators and languages. ------------------------------------------------------------------------------------------------------- UVM-ML Open Architecture: Status, Use, and Disclaimers This section provides guidance and status regarding the use of the UVM Multi Language Open Architecture solution. The UVM-ML Open Architecture package is an open source solution, developed jointly by AMD and Cadence. We welcome feedback including suggestions for improvements. For any feedback or questions, please contact Use and Disclaimers: Licensing: This package is an open source library, protected under the Apache license (see legal clause at the bottom). Access: This package is available as early access to the verification community, and therefore changes to its content and behavior should be expected. Backward compatibility cannot be guaranteed. Changes are expected to take place when the verification community jointly refines the solution, to fit user requirements. We will aim, however, to provide help in adjusting to changes. Quality: this package is still under development. It is being tested and regressed with all active versions of Incisive and with the Accellera OSCI simulator before being released. The user needs to be aware of the simulator version on which the solution is tested. AMD tested the open source solution on other commercial simulators. Issues reported to AMD and Cadence will be addressed. Standardization: This package is not a standard. However, it is available as open source to all potential users. Support: Since this is not a product, it does not have a committed level of product support. We will provide help via the UVMWorld community on Accellera where the source code is posted. For Cadence customers, Cadence will provide direct support as needed. Note: the model described above is similar to how the very successful OVM and UVM-1.0ea (early version) were provided in the beginning. We believe you can gain significant value from access to this solution, and also be able to participate in developing it to ensure it addresses your needs. ------------------------------------------------------------------------------------------------------- What's new in each version For the full listing and more details please see the release-notes.txt file at the top of the release package. Please note that the items in red might require some changes on the user's side while upgrading to this version, please read these items carefully in the release notes. 1.6:Fully qualified with IES versions 14.2,15.1 and 15.2. UVM-SV 1.2 is now fully supported (please read RELEASE_NOTES.txt under ml directory for more details). When working with Incisive 15.2, the user can take some steps in order to skip compiling the e part of the adapter (this might be important for users that compile other e code on top of Specman, like VIP). The steps are documented in the UVM-ML OA user guide under: "Linking the Specman UVM-e Adapter From Incisive Version 15.2 On". OSCI 2.3.1 is now supported instead of OSCI 2.3, meaning that the supported OSCI versions are: 2.3.1 and 2.2. gcc 4.8.3 is now supported [*]1.5.1: Fully qualified with IES versions 14.1,14.2 and 15.1. Early adopters UVM-SV 1.2 support for IES (please read RELEASE_NOTES.txt under ml directory for more details). UVM-ML tcl commands are now available from Specman with all supported simulators. UVM-ML tcl commands are renamed (they all start with uvm_ml prefix, followed by a space and the command name, e.g uvm_ml print_tree). The old names are still supported. Pre-compiled UVM-SC parts for IES were eliminated. Examples are enhanced and extended. Updated the Backplane API version number. [*]1.5: New debug commands in IES to print the UVM-ML tree, port connections, and port registrations. Brand-new documentation including User Guide, Reference Manual and more. Support for IES reset in UVM-ML environment. Support for sharing uvm_events and uvm_barriers between UVM-SV and UVM-SC. Support for +UVM_TESTNAME in all simulators and languages. Passing tlm_generic_payload transactions via analysis ports. Several ASI SystemC enhancements: Automated synchronization, ML-registering of SC TLM2 sockets. Reorganized examples to make them more useful. Enhanced and simplified installation and setup. Fully qualified with IES versions 13.2, 14.1, and 14.2. [*]1.4.4: "Phase Debug" feature, for setting breakpoints at the beginning or end of UVM-ML phases (see the Integrator User Guide for details). Currently this works only for IES. Added support for the generic UVM SV syntax, uvm_config_db#(T), so that it now works also for ML configuration Improved the way to run the demo examples and to learn how to run UVM-ML Reduced the amount of ML enabling modifications introduced into the local version of UVM-SV (1.1d), by enhancing the UVM-SV adapter implementation The e macro uvm_ml_stub_unit now directly sets unit attributes hdl_path() and agent(), thus saving the user a need to add auxiliary string fields Improved the handling of UVM-ML bitness (once users select 32 or 64 bit mode, the library and all examples will run in that mode) Enhanced sequence layering capabilities Enhanced the test_env.csh script to provide more validity testing of the user's environment and to provide better suggestions how to fix issues irun_uvm_ml.*.f option files were reorganized (including a name change): IES irun invocation options were grouped into several option files, reflecting the usage context, and adding comments to clarify their meaning This release might require some changes on the user's code while upgrading to this version, see details in the release_notes.txt” [*]1.4.2: Fully qualified with IES version 14.1 Enables usage of Cadence UVM extensions on top of UVM-ML OA Support for UVM ML configuration tracing on the SV side, activated by the +UVM_CONFIG_DB_TRACE command-line option Added new backplane API functions enabling the time notification (wakeup) service and updated the backplane API version number Updated the sequence layering examples. The code is simplified and type conversion using mltypemap is demonstrated Eliminated the UVM SV warnings Mechanism to recognize whether OSCI was compiled with pthreads and compile the custom sc_simcontext.cpp accordingly New examples showing basic TLM communication Default installation is 32bit instead of 64bit Setup and install scripts renamed UVM-SC has been updated with a standalone phase controller that can run through the common and UVM phases. In addition user defined schedules, which can be synchronized with the standard UVM phases, are supported as well. Enhanced UVM-SC to support run_test() in the SC-standalone mode (not collaborating with other frameworks) [*]1.4: Methodology and examples for sequence layering across languages Enhancements in how unified hierarchy works Support for uvm-1.1d (in place of uvm-1.1c) Addition of a portable UVM-SC adapter. [*]1.2.2: Simulator independent and tested to run on several simulators Architected to be highly modular and extensible A new architecture providing a Backplane that connects Frameworks (where Frameworks can be of different languages or methodologies) Three examples of language frameworks are provided: UVM-SV, UVM-e, UVM-SC Enables creating a unified hierarchy of components of different frameworks Multi-Language configuration Support of TLM1 and TLM2 communication between all the provided frameworks Enhanced synchronization of test phases and delegation of phasing control to a designated framework
  22. To view this announcement on the IEEE web site click here. Purpose Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry. Need for the Project As the electronics industry builds more complex systems involving large numbers of components, the challenge of verifying such systems multiplies by orders of magnitude. In order to bring costs and time to market down, standardization must happen to enable as much modularity and reuse across verification components as possible. The UVM standard will propagate an API that will manage this explosion in verification complexity, allowing the entire industry to write and reuse verification components both (a) internally in companies having geographically widespread teams, and (externally between vendors and user companies in the electronics industry, who are developing, selling and using verification components Call for Contribution Please review the IEEE P1800.2 ™ PAR and, if you are interested in participating, Register for the first working group meeting scheduled to occur on August 6th, 2015 from 12pm – 2pm Eastern Daylight Time (EDT) / 9am – 11am Pacific Daylight Time (PDT). Please feel free to connect with the Working Group Chair, Thomas Alsop at or IEEE-SA staff Jonathan Goldberg at directly for further information.
  23. Hi, I am using uvm_resource_db to set and get any component configuration. But I am getting an error saying configuration object is not found. Its something that its not able to get the config object from configuration space. In env build_phase, I do set the configuration as below: uvm_resource_db#(io_config)::set("io_agent_0*","io_agent_config",m_io_config,this); And in io_agent, below code is used to get the configuration: assert(uvm_resource_db#(io_config)::read_by_name(get_full_name(),"io_agent_config",cfg,this) else uvm_report_fatal("io_agent","not able to get the configuration object"); Kindly let me know if there is anything wrong in the above usage. And also, can I do setting configuration through uvm_resource_db and getting it through uvm_config_db. Thanks A.Sunitha
  24. a usual way to do it is to create a wrapper object and push the wrapper into config_db. Then get this wrapper object from config_db and assign it to the virtual interface pointer (not mentioning the details here) Creating the virtual interface container wrapper parameterized to the strongly typed interface helps here. but in the uvm component, a pointer needs to be created for the parameterised interface. If not wanting the classes to be parameterized, how the virtual interface handle can be created without specifying the parameter as either a default parameter in base class or override is necessary for creating handle?. The component will get the wrapper object from config_db and assign it (the virtual interface in the object) to the virtual interface pointer Thanks.
  25. This is a online training batch taught by experts working in Semiconductor Industry. Course starts with System Verilog and covers advanced level UVM. Course schedule is for 2.5 hours on Sat and Sun for 7 weeks. Graduates and working professionals can benefit from this training. Next batch starting on July 11th, 2015! For more details please email Course schedule is for 2.5 hours on Sat and Sun for 7 weeks. Graduates and working professionals can benefit from this training. For more details please email