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sathyakiran.p posted a topic in UVM (Pre-IEEE) Methodology and BCL ForumHi, we see different kind of failures when we run simulations, like assertion error, uvm_error. How do we report outside UVM errors in report phase to give the TEST STATUS? I am getting some psl/ovl/sva assertion errors, but, UVM part is not reporting any error. how do I report test STATUS?? Thanks, Satya