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Found 27 results

  1. Hello, I'm trying to develop a memory that supports custom bytes/words. In the usual case, the byte is 8bit and word has 4 bytes (assuming 32bit data-path). Now, in embedded, it's possible that the byte is 12bit and word has 2 bytes (24bit data-path). For 12/24 integers, I can use sc_uint<12> or sc_uint<24>. So, my question is: Is there any helper function that stores/loads a custom int into the generic payload? If not, are there any rules to follow? Thanks.
  2. Hi I have doubt about TLM Phase. Do i need use tlm phase in this specific order always (BEGIN_REQ,END_REQ,BEGIN_RESP and END_RESP)?? And if yes, what should be done when I send a BEGIN_REQ from the master side but get END_RESP from the slave side. (Should just stop the transaction??) Please help me out with this doubt
  3. I have array of target sockets. sc_vector<target_socket_type> m_target_socket; which are bind to tagged nonblocking forward function and here is declaration of the function sync_enum_type my_forward_function(int port_id,...) { m_peq.notify(trans, phase, t); return tlm::TLM_ACCEPTED; } registered callback for peq is peq_cb. Is there a way for my callback to to know port_id? I need to send END_REQ back on same port's backward path, but I need to know id. Thanks
  4. I need to create a TLM module (that here we will call top_level) containing an array of TLM target modules (defined by class reg). As a consequence, the top_level module should implement the tlm_bw interface, and contain an array of initiator sockets, each bound to a target socket of the reg modules. Is it possible to implement this hierarchy by using the sc_vector construct? Here is a snapshot of the code that I am trying to implement, to give a clearer idea: Top level #include "reg.h" class top_level : public sc_module , public virtual tlm::tlm_bw_transport_if<> { private: sc_time time; sc_vector<reg*> register_file; tlm::tlm_generic_payload reg_trans; public: sc_vector <tlm::tlm_initiator_socket<>*> initiator_socket; ... }; Target module: class reg : public sc_module , public virtual tlm::tlm_fw_transport_if<> { public: tlm::tlm_target_socket<> target_socket; virtual void b_transport(tlm::tlm_generic_payload& trans, sc_time& t); reg(sc_module_name name_); ... }; When trying to compile, the compiler returns this error: error: ISO C++ forbids declaration of ‘sc_vector’ with no type error: expected ‘;’ before ‘<’ token referring to both the instances of sc_vector, as if neither my class nor the initiator_socket class were recognized as datatypes... Best regards, S.
  5. Hi all. I'm testing some codes to better understanding tlm. In this moment I have a block with this variable : std::map <tlm::tlm_generic_payload*, unsigned int> queue; Basically a place when I store my transactions using trans pointer as key. This variable is accessed by 2 threads. On as input and one as output. Input is fast, output is slow. Threads Input wait until a location (I check my max size) is free and fill it. In system C I used sc_mutex to check lock and check it every X ns (wait(X,SC_NS)). In tlm I don't want to used fixed time but wait until a location is free. Is there a simple approach to do this or I need to use sc_mutex or similar to share variable among multiple process ? Thanks for every suggestion. I need it!
  6. Hi Accellera forum, I have an NoC Mesh that is using convenience tagged socket for its North, South, West, and East socket. Then I also have initiator socket and target socket, to connect this NoC node to the processor or memory or to any other peripherals in my SystemC-TLM platform. My question is can we implement more than one blocking transport function inside one SystemC module? Because the functionality of N,S,W,E socket are different with the target socket one. Several transaction are passed to the correct destination node, until at one point there is a transaction that has so big transaction.get_address( ) value (0xffffffe0) which leads to simulation error. It is clear that the transaction address can't be routed to any of the node because there isn't any address that large inside the platform architecture. I have test the application using processor - decoder - memory, and it works just fine. My best guess is that maybe my socket implementation is not correct 100%. Appreciate any suggestion and feedback. Thank you. Regards, Arya.
  7. Good day, I have a question regarding how to determine the appropriate delay value for the wait( ) function call. In the target b_transport callback, we can add delay to the simulation time by passing delay amount to the wait( ) function. In simulation that uses quantum and temporal decoupling that targets super fast instruction accurate simulation, the timing does not have to be very detail (loosely timed). With or without delay in the target callback function will not cause any functional inaccuracy and still we could produce the platform that can support firmware/software development. Still if we want to put a delay to the wait( ), how can we determine the appropriate delay value for the function parameter? Thank you. Regards, Arya.
  8. Hi all, I think I have located a bug in the uvm_tlm2_generic_payload class and I would like to file it. I did follow the instructions in this document: http://accellera.org/images/community/uvm/Reporting_bugs_enhancement_requests_UVM_Apr2014.pdf Is this still the recommended way of filing a bug? /JSA
  9. Hi, I'm newbie to SystemC TLM, coming from SystemVerilog UVM world. I would like to model our RTL in SystemC using TLM2.0 to speed up our Software Development process. Our RTL is not memory mapped bus architecture and we would like to use custom transaction class instead of generic payload. Is it possible to do that using TLM2.0? If yes, could you please provide me with an example. Also, I have four TLM ports communicating with each other in the same model. How does one b_transport method works with all four ports? Is it a good idea to make a model in SystemC rather than having it in SV UVM? Thanks Zubin
  10. Hi all, After developing a virtual platform using SystemC with TLM, and also several peripherals (IP) model in high-level (LT), I realised that if in RTL design there is a UVM to say that the design is "okay". How about in high-level? Is there any methodology that we could adopt? If there is none, may I ask for your suggestion on how to verify our own SystemC TLM (LT) design? The SystemC Verification subforum seems to be obsolete, so I posted it here. Really appreciate any kind of advice and solution. Thank you. Regards, Arya.
  11. What is SystemC ? Roughly I think it's a language or more specifically a library useful to create software representation (not synthesizable) of an hardware at an abstarction level higher than RTL (- which is synthesizable). Please correct me if I am wrong, Also help me with some standardize definition. What is architectural exploration ? And How SystemC and TLM is useful for it ? If someone working in a systemC domain, could they classify themselves as a software engineer ? Where does it classify ? Which is more appropriate semiconductor industory , EDA or ESL domain ? How someone working in systemC explains their Job to someone non-technical person ? PS: If this question is not appropriate for this forum, then please help me with some details where I could find my answers. I believe these questions must be answered before someone starts learning it.
  12. Hi guys , I'm representing a systemC TLM platform in IP-XACT, I finished with systemC modules. Now, each systemC module representing a functional hardware block has to be attached to a c++ object in order to represent some non functional information. Please, is it possible to represent this information within IP-XACT ?? Thanks
  13. Hi All, I'm quite new to TLM and have just joined this forum. I'd appreciate if you could help me to clarify one probably very simple question. I have N targets and one initiator. Each target handles transactions of particular priority. I need to analyze several transactions, arriving at these targets in one delta-cycle, select one with the highest priority and send it from the only one initiator. Priorities can change dynamically. Can you please share your ideas on that? Thank you in advance, Evgeniy
  14. Hi All, I'm new at this forum. I encounter problem with circular_buffer. Let me explain it on simple example (code is from circular_buffer.h): I have a circular_buffer with few elements . After read one of them element is destroyed: template < typename T > T circular_buffer<T>::read() { T t = read_data(); buf_clear( m_buf, m_ri ); increment_read_pos(); return t; } template < typename T > inline void circular_buffer<T>::buf_clear( void* buf, int n ) { (static_cast<T*>(buf) + n)->~T(); } } // namespace tlm ... but In dectructor all elements are destroyed ... again template < typename T > circular_buffer<T>::~circular_buffer() { for( int i=0; i < used(); i++ ) { buf_clear( m_buf, i ); //!!!! } buf_free( m_buf ); } This case GPF's randomly. I notice that when I change desctructor code to for( int i=m_ri; i < used() % m_size; i++ ) { problem disappears I'm using SystemC 2.3.0 Is this a bug in TLM sources or I'm doing something wrong ? Radek
  15. hai to all Iam karthik,doing my masters in VLSI DESIGN ,i found my interest in system level design and i wish to do project in systemcTLM based simulation.As a starter ,learning systemC language and i want to learn how systemc TLM differ by verilog,VHDL and other languages by results.i.e by simulation...kindly guide me regarding by suggesting some projects or papers in these domains.. keywords:co-simulation,systemc based simulations..
  16. Hi, I am currently considering to enhance a virtual prototype TLM model with AMS models mainly in order to add more accurate models of the power management part including accurate battery model, voltage regulator control loops... We have stringent simulation performance criteria for the virtual prototype since it needs to run SW on a complex HW model. If we just use simple ams2de ports to interface the tlm part with the AMS model we risk to brake the whole VP simulation. I am missing some guide to properly define the interface between the AMS part and the TLM part. I found attached screenshot from SystemC AMS extension - alignment with SystemC-TLM Workshop slides which depicts an approach to define that interface. However I am not so clear about how it can be implemented. The question here is: Is there any implementation guide or source code template for a simple example on how to define the interface between AMS and TLM? @Martin: I would really appreciate any hint ! Many thanks! Ismael, systems engineer big semiconductor company
  17. Hi everyone, For a processor model, I need to be able to reset or kill a transaction sent across an interface and stored in a Payload Event Queue. How can I do that? If I initiate a transaction like this : tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; tlm::tlm_phase* trans_phase = new tlm::tlm_phase; sc_time* delay = new sc_time; tlm::tlm_sync_enum* transStatus = new tlm::tlm_sync_enum; *trans_phase = tlm::BEGIN_REQ; *delay = SC_ZERO_TIME; // Or any delay trans->set_command(tlm::TLM_WRITE_COMMAND); trans->set_dmi_allowed(false); trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); *transStatus = InitSocket.nb_transport_fw(*trans, *trans_phase, *delay); How could I, afterwards and before the specified delay has elapsed, kill this transaction or remove it from the target Payload Event Queue? Can I keep a copy of the 'trans' pointer to reset the transaction content if needed? Thank you for your help! Regards, J-B
  18. Good day. I am new to SystemC and TLM. Here I am implementing producer-consumer model with a bus and memory model. The synchronization between producer-consumer is done using semaphore. I add DMI feature to the simulation. So the idea is to give producer direct access to the memory region. The same goes for the consumer. What I expect from doing this is to gain faster simulation time. However, at some point of my experiment it shows that using DMI takes longer simulation time. Is this normal to happen? Or I might implement the DMI in the wrong way? Thank you. Best regards, Li.
  19. Hi All: Get to implement a timer module in SytemC-TLM. And it is at LT level. The Time used for interrupt generation is from sc_time_stamp. My current implementation is using TLM payload event queue, which means the timer caculates the expected wait time for the request and do "notify(x ns)" for the payload event queue. Which the drawback is: 1.When I add the cancel function for a ongoing time request, I can't delete the "time request" from the event queue. I do a workaround like saving some tags when the timeout happened to achieve the "cancel" 2.When I add a stop function for the timer, I also need a tag and did lots of workaround in order to fullfil the stop/re-start function. So, is there any foward way to do this? If i do my own queues instead of using Payload event queue(But I guess I still need to use notify(x ns) in some way), may I somehow delete a ongoing requests? Thanks BR
  20. I am learning UVM. So far I was able to create the following environment for my DUT. Agents with monitors, drivers and sequences for all of the input-output interfaces from my DUT. A top level UVM env. Sequences to send valid data to DUT. I yet to implement scoreboard. I'm having some trouble to understand how to handle scenarios like following: For one of my tb->dut interfaces, TB needs to wait for an event (or transaction) from DUT. Once it receives the transaction from DUT, TB needs to send back a response. What is the best way to implement this? How can I monitor DUT transaction from sequence? I assume I need to wait for an event or something similar which will tell me that DUT has a new valid output in its interface. My agents have monitors which will monitor any new output signals from DUT. So, do I need to somehow bring this data from agent's monitor to my test/sequence class? I know that monitor has an analysis port and it can be used to send received data to scoreboard for checking. So, do I need to use the same port to read DUT output data, create valid response and send it to DUT? Thanks!
  21. Hi, I am new to using the TLM2.0 methodology, and I was trying to model a Mater and Slave to work with AXI buses. I wanted to use a transactor for that purpose, and was wondering if System C provides any libraries where I can instantiate a Transactor which converts from the TLM2.0 GP To the AXI protocol so that I can connect it to my bus. Also, I was wondering if you could tell me a little more about something called the FT_PROTOCOL_TAG , associated with sockets in the system C modelling Library ? Thanks Sukriti Kapoor
  22. Hi Can anybody please tell me how to write a transactor for an existing System C model? I can write a systemC model as well as a LT TLM model. But i don't know how to interconnect both of them using ports. Any valuable help would be appreciated. Thanks
  23. We are using TLM to pass transactions from SystemVerilog to SystemC. I have two cases where I am stuck. Actually, it is the same case, but I have two angles to my question. 1) Is it possible to still use a TLM setup, but without a transaction type. (I realize that this is contradictory to the acronym.) A c-model has a debug function which takes no input arguments. So, when the SV testbench runs into a problem, it can call this function in the SystemC/c-model. As all of our connections now are sc_port/sc_export, with TLM, I'd like to stick with that flow if possible, rather than adding DPIs/VPIs/(PLIs) or any other mechanism to communicate between languages. However, since the function has no input arguments, I don't need a transaction type. So, is there a way to do a TLM call without a transaction type? (I suppose I could just use another transaction type and ignore the data.) 2) Imagine the above c-model input function that takes no input arguments. Let's say now that the c-model function takes a single integer as its input. So, now I do have a transaction type, but a very simple one. It seems like overkill, but do I still need to define matching .h and .svh (that extends uvm_sequence_item) transcation types and the related do_pack, do_unpack, etc. routines? It seems like overkill. I suspect that I must, if I want to use TLM. (Given that the answer to this question must be, yes, does anyone out there just use a generic grab-bag transaction type for cases like this?) //my thought of passing a transaction which is just an int in sv tb: uvm_blocking_put_port #(int) sb_debug_call1_to_cmodel; in sc c-model public tlm::tlm_blocking_put_if<sc_int <32>> //or smthg like that Any thoughts? I know I just need to refresh myself on DPIs, but answers to the above question are welcome.
  24. Hi all, I'm facing an issue when using the UVMconnect package. The simulator complains about missing fields: # ** Error: (vsim-3567) /share/uvmc-2.2//src/connect/sv/uvmc_tlm1.sv(652): No field named 'm_get_if_mask'. # Region: /uvmc_pkg::uvmc_tlm1_port_proxy::uvmc_tlm1_port_proxy__1 # ** Error: (vsim-3567) /share/uvmc-2.2//src/connect/sv/uvmc_tlm1.sv(652): No field named 'm_get_if_mask'. # Region: /uvmc_pkg::uvmc_tlm1_port_proxy::uvmc_tlm1_port_proxy__1 # ** Error: (vsim-3043) /share/uvmc-2.2//src/connect/sv/uvmc_tlm1.sv(652): Unresolved reference to 'm_get_if_mask'. # Region: /uvmc_pkg::uvmc_tlm1_port_proxy::uvmc_tlm1_port_proxy__1 # ** Error: (vsim-3567) /share/uvmc-2.2//src/connect/sv/uvmc_tlm2.sv(412): No field named 'm_get_if_mask'. # Region: /uvmc_pkg::uvmc_tlm2_port_proxy::uvmc_tlm2_port_proxy__1 # ** Error: (vsim-3567) /share/uvmc-2.2//src/connect/sv/uvmc_tlm2.sv(412): No field named 'm_get_if_mask'. # Region: /uvmc_pkg::uvmc_tlm2_port_proxy::uvmc_tlm2_port_proxy__1 # ** Error: (vsim-3043) /share/uvmc-2.2//src/connect/sv/uvmc_tlm2.sv(412): Unresolved reference to 'm_get_if_mask'. # Region: /uvmc_pkg::uvmc_tlm2_port_proxy::uvmc_tlm2_port_proxy__1 I have two connections in my desing, one TLM2 socket connection and one TLM1 analysis port connection. The SystemVerilog transaction item (my_item) has the packing methods implemented in the class, on SystemC side (my_sc_item) I use converter specialization for conversion. For example for the TLM2 connection, this is the code on SV side: uvm_tlm_b_initiator_socket #(my_item) initiator; initiator = new("initiator", this); uvmc_tlm #(my_item)::connect(initiator, "uvmc_channel"); And on SC side: tlm_utils::passthrough_target_socket<module, 32, my_sc_item> target; uvmc::uvmc_connect(target, "uvmc_channel"); I used UVMconnect successfully before, thus I wonder what's wrong in this case. Any idea where those errors comes from? Thanks, Thomas
  25. Hi, i would like to draw the SysML diagramm of my implemented TL-Model. Which type of Diagramm should i use for representing: Components (Initiators, targets, interconnects) with the socket connections? : Block diagramm oder internal block diagramm? the behavior of a process: state machine diagramm? Are there any examples? Thank you so much for the help