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Found 94 results

  1. Saw the UVM-SystemC-1.0-beta1 download link, try to install it, but according to the INSTALL file, I can't find "configure" in the package. How could I install it?
  2. clock problem

    Hi all, i'm implementing a timer/counter(8-bit) that should not increment on every clock and i'm not supposed to provide any input clock port . But i need clock period in my design so my question is " How would i provide clock period(through constructor)?" here is the link to my working code on EDAplayground : http://www.edaplayground.com/x/4_dY if there is any problem in my code please feel free to tell me. regards, jatin
  3. Hi all, is there any way to implement the intra assignment delay in systemC without using sc_event()? for example : in verilog we write out = #10 in1 + in2; // intra assignment delay. how would i implement the same in systemC? regards, jatin
  4. Hello, I am using SystemC 2.3.0. I am wondering how I can profile the SystemC library. I found we can use options like "--enable-debug" and "--disable-optimize" for debugging and optimization, respectively, but I was unable to find such an option to enable profiling. I need to use gprof and pass "-pg" options when building SystemC. Any help is greatly appreciated! Thank you in advance.
  5. I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals. I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish. So would someone let me know what's the right way to handle the clock and reset signals?
  6. Hey, Kahn Process Networks are defined by the usage of unbounded FIFOs with blocking reads and non-blocking writes. I read on several sources that KPN with bounded FIFO size (i.e. blocking read and blocking write) can be implemented with SystemC (e.g. Grötker et al). It seams that the event based scheduler in SystemC behaves different like data-driven scheduler or a demand-driven for KPNs. I simulated the networks of Park's Dissertation shown on page 36 and 42 which should end up in an artificial deadlock (deadlock which occurs because of blocking write). A global artificial deadlock in SystemC would result in no scheduled events, and therefore, the simulation should be stopped. However, even with buffer size 1 for all FIFOs both examples from Park are continuing with execution: Page 63: http://www.edaplayground.com/x/6Mfi Page 42: http://www.edaplayground.com/x/4jLZ Note that edaplayground exits because of to much output. If you want to test it you better download it and run it on your PC. Apparently, the SystemC scheduler finds automatically a schedule for the KPN such that no artificial deadlocks occur. My question: is there an example where I could also see an artificial deadlock in SystemC? Thanks and Regards Matthias
  7. Hi, I am getting the same sequence of random numbers every time I run my SystemC code ... there is too much code to post here, so I will attempt to describe what I am doing ... I have written a DUT (SC_MODULE) with 9 input ports and I have written a Driver (SC_MODULE) to drive one of those ports, I have instantiated 9 Drivers and 1 DUT in sc_main ... the Driver uses rand() ... Each Driver produces the exact same sequence of random numbers ... I didn't some looking on the C++ forums and tried the following ... 1. Adding srand(time(NULL)) to the Driver ... but it won't compile 2. Adding srand(time(NULL)) to just sc_main ... compiled ok but made no difference 3. Adding srand(time(NULL)) to the constructor, I added it to the Driver SC_CTOR ... compiled ok but again made no difference Those were the only possible solutions I found on the C++ forums ... I didn't see anything related on here ... As always any and all help would be greatly appreciated :-)
  8. I am a novice at SystemC (some OOP background but not much) ... I am getting an error for the code below ... ../src/xor2.h:20:31: error: invalid initializer for array member 'nand<2> xor2::nand2 [4]' I have much more complicated but netted my problem down to this much simpler and smaller example ... #include "systemc.h" template <int width> SC_MODULE(nand) { sc_in<bool> A[width]; sc_out<bool> F; void nand_func() { F.write(!and_reduce(A)); } SC_CTOR(nand) { SC_METHOD(nand_func); sensitive << A; } }; #include "systemc.h" #include "nand.h" SC_MODULE(xor2) { sc_in<bool> A, B; sc_out<bool> F; nand<2> nand2[4]; sc_signal<bool> sig1, sig2, sig3; SC_CTOR(xor2) : nand2("NAND2") { nand2[0].A[0](A); nand2[0].A[1](B); nand2[0].F(sig1); nand2[1].A[0](A); nand2[1].A[1](sig1); nand2[1].F(sig2); nand2[2].A[0](sig1); nand2[2].A[1](B); nand2[2].F(sig3); nand2[3].A[0](sig2); nand2[3].A[1](sig3); nand2[3].F(F); } }; I would greatly appreciate any help and suggestions of ways to use multiple template'd modules in this way ... xor2.h nand.h
  9. Hi everyone, my initiator is writing to a specific register but I want to block the initiator if a certain bit of the target register is set (1). is there a way to do that?
  10. Hello, Is there a way to generate execution trace for a SystemC project? Thanks, R.Adiga
  11. Hello All, I am working on SystemC-UVM based testbench. I have created UVM based testbench using UVM code generator. Here I am using three different agents in UVM generator which I have defined as a part of the configuration file which was further being provided to UVM code generator to generate test bench skeleton. And here, in of the agent driver, the code snippet is as: // Drive the inputs of the DUT UVM_INFO(this->name(),"Driving transaction:",0); req.print(); // TODO put your code here But when I try to read the value in my test-case, then I see an error as: And this error is observed inside print() function, once I comment the line "req.print()" from the above snippet the error is no more observed and my test-case runs fine.
  12. Hello There is an existing model with tlm1.0 sockets - sc_port and sc_export. Is it possible to bind these sockets to tlm2.0 initiator and target sockets? If yes, then what is the conversion procedure involved? I'm new to SystemC, any help/insight on this is appreciated. Thanks.
  13. Hello, I'm just starting off with TLM-2.0 and would like to explore more about the use cases for byte_enable_ptr. In TLM manual, I see that " A value of 0 shall indicate that that corresponding byte is disabled, and a value of 0xff shall indicate that the corresponding byte is enabled"; Does this mean that we can switch between 0xff and 0x0 if required for every transaction? TLM manual also states that Byte Enable can be used to create burst transfers, can anyone please explain this? Thanks, R.Adiga
  14. Folks, I have requirement to calculate bandwidth per socket. This means I need to count how many transactions were sent on a given socket, and also pass clock information. Are there any example of customizing socket where I can calculate these things and print of at the end of the simulations.
  15. systemC

    Hi all, im a a student and my project is about systemC, im searching for a freelancer who can help please send to me a private message. thank you
  16. Support for C++11/14 in SystemC 2.3.2

    In the SystemC 2.3.2 review thread Ameya Vikram Singh (@AmeyaVS) reported the following observation: I'll open a separate topic to discuss the details.
  17. openCv systemC

    hi all, i want to integrate systemC and openCv in visual studio 2015 to process images for motion detector system. it is possible to do that ? thanks
  18. SOLVED: Nevermind, I made some mistakes in calling the wrong methods for writing/reading from ports. Thanks for your attention anyway! I'm trying to implement this example of a memory and a cpu that are communicating. CPU <==> MEM The modules use a single bidirectional data-line for reading/writing. I defined a signal in sc_main: sc_signal<int,SC_MANY_WRITERS> s_memdata; which I connect to the CPU and MEM module through their ports: sc_inout<int> p_memdata; The CPU is writing to the s_memdata signal: p_memdata.write(getrnddata()); As well as the memory: p_data.write( m_data[ m_curAddr ] ); In the debugger I see that the m_curAddr is changing correctly. Yet, the VCD file shows that the signal "data" is not changing when the "address" is changed (as shown in the figure) Actually, the "data" only changes when the cpu is writing to it, not when the memory is. (I was not able to show the function read/write signal because the enum didn't show in the VCD file). It seems to me that there is something going on with the two modules writing to the same channel. I've noticed sc_logic that introduces Z and X values, is this the appropriate way? edit: I've created a simple proof of principle with two writers that talk to a single sc_signal< bool, SC_MANY_WRITERS > which seems to work. So the problem is something different. Thanks for any help or tips. mem_tb.cpp int sc_main(int argc, char* args[]){ Memory * mem; CPU * cpu; mem = new Memory("main_memory"); cpu = new CPU("cpu"); /* sgn */ sc_signal<Memory::Function,SC_MANY_WRITERS> s_memfunc; sc_signal<Memory::RETSignal> s_memsig; sc_signal<int> s_memaddr; sc_signal<int,SC_MANY_WRITERS> s_memdata; sc_clock clk; mem->p_addr(s_memaddr); mem->p_func(s_memfunc); mem->p_data(s_memdata); mem->p_sig(s_memsig); cpu->p_memdata(s_memdata); cpu->p_memaddr(s_memaddr); cpu->p_memsig(s_memsig); cpu->p_memfunc(s_memfunc); mem->clk( clk ); cpu->clk( clk ); std::cout << "Running, CTRL+C to exit..." << std::endl; sc_trace_file * trace = sc_create_vcd_trace_file("trace"); sc_trace(trace, s_memaddr, "addr"); sc_trace(trace, s_memdata, "data"); sc_trace(trace, s_memfunc, "func"); sc_trace(trace, s_memsig, "sig"); sc_start(); sc_close_vcd_trace_file( trace ); return 0; } cpu.h #include <systemc.h> #include "memory.h" #include <boost/random.hpp> SC_MODULE( CPU ) { public: sc_in<bool> clk; sc_in<Memory::RETSignal> p_memsig; sc_out<Memory::Function> p_memfunc; sc_out<int> p_memaddr; sc_inout<int> p_memdata; SC_CTOR( CPU ) { SC_METHOD(exec); sensitive << clk.pos(); dont_initialize(); SC_METHOD(done); sensitive << p_memsig; dont_initialize(); m_waitmem = false; rng.seed( time(NULL) ); dist = new boost::random::uniform_int_distribution<>(0,1<<16); } private: boost::random::mt19937 rng; boost::random::uniform_int_distribution<> *dist; bool m_waitmem; int rand(); Memory::Function getrndfunc(); int getrndaddr(); int getrnddata(); void exec(); void done(); }; cpu.cpp Memory::Function CPU::getrndfunc() { switch( rand() % 2 ) { case 0 : { return Memory::FUNC_READ; } default : { return Memory::FUNC_WRITE; } /* 1, and all other cases... */ } } int CPU::getrndaddr() { return rand() % MEM_SIZE; } int CPU::getrnddata() { return rand(); } int CPU::rand() { return (*dist)(rng); } void CPU::exec() { if(m_waitmem) return; int addr = getrndaddr(); Memory::Function f = getrndfunc(); p_memfunc.write(f); p_memaddr.write(addr); if(f==Memory::FUNC_WRITE) p_memdata.write(getrnddata()); } void CPU::done() { if( p_memsig.read() == Memory::RSIG_NONE ) return; m_waitmem = false; p_memfunc.write(Memory::FUNC_NONE); } memory.h #define MEM_SIZE 512 SC_MODULE( Memory ) { public: enum Function { FUNC_NONE = 0, FUNC_READ = 1, FUNC_WRITE = 2 }; enum RETSignal { RSIG_NONE, RSIG_READ_FIN, RSIG_WRITE_FIN, RSIG_ERR }; sc_in<bool> clk; sc_in<Function> p_func; sc_in<int> p_addr; sc_inout<int> p_data; sc_out<RETSignal> p_sig; SC_CTOR( Memory ){ SC_METHOD(execute); sensitive << clk.neg(); m_clkCnt = 0; m_curAddr = 0; m_curData = 0; m_curFunc = Memory::FUNC_NONE; m_data = new int[MEM_SIZE]; m_writesCnt = 0; m_readsCnt = 0; m_errorsCnt = 0; m_errorCode = 0; } ~Memory(); private: int m_clkCnt; int m_curAddr; int m_curData; Function m_curFunc; int* m_data; int m_errorCode; int m_writesCnt; int m_readsCnt; int m_errorsCnt; RETSignal read(); RETSignal write(); void execute(); }; memory.cpp #include "memory.h" Memory::~Memory() { delete[] m_data; } Memory::RETSignal Memory::read() { if( m_errorCode ) { m_errorsCnt++; return RSIG_ERR; } p_data.write( m_data[ m_curAddr ] ); m_readsCnt++; return RSIG_READ_FIN; } Memory::RETSignal Memory::write() { if( m_errorCode ) { m_errorsCnt++; return RSIG_ERR; } m_data[ m_curAddr ] = m_curData; m_writesCnt++; return RSIG_WRITE_FIN; } void Memory::execute() { if( m_curFunc != FUNC_NONE ) { m_clkCnt++; if( m_clkCnt == 100 ) { RETSignal retSig = RSIG_ERR; switch(m_curFunc){ case FUNC_READ : { retSig = read(); break; } case FUNC_WRITE : { retSig = write(); break; } default : { /* */ } } p_sig.write( retSig ); m_clkCnt = 0; m_curFunc = FUNC_NONE; } return; } if( p_func == FUNC_NONE ) return; m_curFunc = p_func.read(); m_curAddr = p_addr.read(); m_curData = p_data.read(); p_sig.write( RSIG_NONE ); }
  19. In my project there are several functions which perform SystemC simulations (each has its own declaration prelude and sc_start()). So they are constructed as follows: // first Simulation: sc_signal<double> s1_sim1; .. ControlFoo<double> *cf = new ControlFoo<double>(); cf->Foo_port(s1_sim1); .. sc_start(); // works fine delete(cf); .. // second Simulation: sc_signal<double> s1_sim2; // this leads to an exception The first simulation runs as desired until the sc_stop(). But when I try to declare new sc_signals after the first simulation is completed then it comes to an exception. How do I solve my problem? Best regards Anne (I also asked this on stackoverflow but no response yet. http://stackoverflow.com/questions/42997196/project-with-multiple-systemc-simulations-leads-to-an-exception)
  20. Hi, i am trying to declare an sc_port from which i want to send a struct (ressource) between two different modules. I declared an interface and a channel to implements the send and receive interface methods but i am experiencing two errors. The first one is C2011 'class ' type redefinition, the second one is C2504 base class undefined. Now the Interface is very simple: //comm_interface.h class comm_send_interface : virtual public sc_interface { public: virtual bool send(ressource) = 0; // send a ressource virtual void reset() = 0; // empty ressource list }; class comm_recv_interface : virtual public sc_interface { public: virtual bool recv(ressource &) = 0; // receive a ressource }; The channel where i implement the methods looks like this: //comm_channel.h #include "comm_interface.h" class comm_channel : public sc_module, public comm_send_interface, public comm_recv_interface { private: ressource rdata[9]; int i; //sc_event send_event, recv_event; public: comm_channel(sc_module_name rc_channel) : sc_module(rc_channel), i(0) {} bool send(ressource r); // write bool recv(ressource & r); // read void reset(); //void register_port(sc_port_base & port_, const char * if_typename_); }; bool comm_channel :: send(ressource r) { if (i < 10) { rdata[i++] = r; //recv_event.notify(); return true; } //wait(send_event); return false; } bool comm_channel :: recv(ressource &r) { if (i > 0) { r = rdata[--i]; return true; //read_event.notify; } return false; } void comm_channel :: reset() { i = 0; } And here i declare the sc_port to send and receive the "ressource". #ifndef ROBOT__H #define ROBOT__H #include "systemc.h" #include "ressource.h" //interface #include "comm_interface.h" struct robot : sc_module { sc_port<comm_recv_interface> rinput; sc_port<comm_send_interface> routput; ressource r; void drill(); void insert(); void tight(); SC_CTOR(robot) { //... }; #endif // ROBOT__H Can you help me with the Problem?! Thanks in advanced!
  21. Is there a way to identify each generic payload transactions with id? I need some id that I can print out as my transaction flows from initiator to target via different modules. Thanks
  22. I created vector of fifos: sc_vector<sc_fifo> fifos; and in my constructor: template <unsigned S> class my_chnl : public my_chnl_if, public sc_channel { sc_vector<sc_fifo> fifos; //vectors of fifos //----------------------------------------------------------- public: //----------------------------------------------------------- //constructor //----------------------------------------------------------- explicit my_chnl(sc_module_name nm, unsigned _size = 4) : sc_channel(nm), fifos("FIFO") { fifos.init(S, _size); } ..... I am getting compile error saying that include/sysc/utils/sc_vector.h:634: error: \u2018c\u2019 cannot be used as a function If I do fifos.init(S), it works, but I get default size of 16. How do I set custom size? Any help? Thanks
  23. I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!
  24. I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile. The error message is about the "undefined reference to `m__uvm_report_dpi'. I'm using: GCC 4.5.2 on CentOS 5.11 VCS 2015.09-SP2-3 SystemC 2.3.1 SCV 2.0.0 UVM 1.2 UVMC 2.3.0 Appreciate all the help!
  25. Hi there, I'm an engineering student from Venezuela and working on systemC for a class project. I'm having a bad time trying to make a tri-state buffer model on system C. I know there is sc_logic and sc_lv but I just don't know how to work with this two data types. I'm working a project (a microprocessor) and I need to model a tri-state module to hook up with my registers so I'll be able to have control on the data coming out of the registers. In case you wonder here is more info https://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Build/implRegFile.html Any idea on how to model a tri-state buffer module?. thanks in advance.
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