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Found 137 results

  1. I have a module which shapes the data and then dump into the memory module depending on if data input is more than Bandwidth. If data input is less than Bandwidth then it will bypass it that means no clock cycle wastage and the way to bypass is only if I can call the process of memory module from shaper module for writing the data. So, is it possible to do what I am thinking? or I can do the bypassing without calling the process of memory module?
  2. Hi, I am trying to model large memories (>8 GB) on a virtual platform that I am working on. I don't think using the C++ 'new' operator to allocate the entire chunk is a good idea. Can someone suggest any methods they think or have used in the past to model such? My memory is going to be very sparse to start with and might start filling up only at a later time. Thanks,
  3. Hi, I wanted to know ,is it possible to trace waveforms in tlm.I tried for alternate ways as it was done in system c earlier also.But i wasnt successful in my attempts. One of the way i tried was by using the init_socket and targ_socket again in top which is completely wrong i guess.I cant reuse the tlm sockets again for my instantiated modules. int sc_main(int argc,char* argv[]) { initiator* init; target* targ; tlm_utils::simple_initiator_socket<initiator>i_top_socket; tlm_utils::simple_initiator_socket<target>t_top_socket; init = new initiator("init"); targ = new target("targ"); init->i_socket(i_top_socket); targ->t_socket(t_top_socket); sc_clock clk1("clk1", 10, SC_NS, 0.5); sc_clock clk2("i_t_clk", 20, SC_NS, 0.5); init->i_socket.bind(targ->t_socket); init->ext_i_clk(clk1); targ->int_t_clk(clk2); sc_trace_file* tf = sc_create_vcd_trace_file("b_transport"); sc_trace(tf, clk1, "ext_clk"); sc_trace(tf, clk2, "t_clk_internal"); sc_trace(tf, init->i_socket, "i_socket"); sc_trace(tf, targ->t_socket, "i_socket"); sc_start(200, SC_NS); sc_close_vcd_trace_file(tf); return 0; } The other way i tried was getting the arguments not matching error i.e arguments support sc_signal type and i am using tlm types.I kno that the compiler is telling the difference in arguments,but whats the alternate solution for this problem ? Can anyone please tellme where am i going wrong and how to trace the transaction exactly ? And Is it really possible to trace waveform in tlm ? Thanks & regards, Shubham
  4. I have recently started using SystemC for my project. I would appreciate if someone could help me with following problem. How can I select part of input port in SystemC? In Verilog it can be done easily by choosing the required bits, e.g., inputPort[3:1] How can I do this in Systemc? I have defined an input port as follows sc_in < sc_int<5> > inputPort; What is the syntax to read bits e.g., [1:3] from inputPort like I did in Verilog? I tried few syntax like inputPort.read({1:3}) but no success.
  5. Hi, I have declared and defined the clock in my example and able to generate and transport the transactions successfullly. As its is a blocking transport interface of tlm,so we are using wait statement. But what i observed here is, i am not able to control the triggering of process by using clocks for both the modules.Thiugh , i am able to controll the thread awakening by using delay statements. What if i want to use clocks to controll the trigger ,thats why i had put them in the sensitivity list. Please let me know,what would be my approach for the triggering by clocks.? do i need to look out for other interface method in tlm or should i go back to system c interface approach ? Please help me out with this. Thanks & regards, Shubham Ps:- I am attaching the code along with the block diagram below,please let me know the solution for it.The block diagram represents 2 blocks of initiator and target modules with clock supplied. Iam able to compile and run the code succesfully,if you get any error while compiling i might have done mistake while copying. initiator.h.txt main.cpp.txt target.h.txt initiator2.h.txt target2.h.txt top.h.txt
  6. Dear all, I need to do floating point arithmetic in systemc. My question is if after I do two floating point addition or multiplication, can I call this api(is_inf()) for the sum or product to determine it is inf or not? The produced results looks correct for me. Like the following sample code ```c num1.negative(sign1); num2.negative(sign2); num1.exponent(exp1); num2.exponent(exp2); num1.mantissa(significand1); num2.mantissa(significand2); //the additiion result result = num1+num2; cout.precision(23); cout << result.is_inf() << " " << num1 << " " << num2 << " " << result << endl; ``` The following are my test samples: The first column is is_inf flag, the second and the third column are the source operands and the last column is the produced result. ``` 1 -3.402823466385288598117e+38 -3.402823466385288598117e+38 -inf 0 0.5 -0.20000000298023223876953 0.30000001192092895507812 0 0.5 -9.9999997473787516355515e-05 0.49990001320838928222656 0 0.5 -0.30000001192092895507812 0.19999998807907104492188 0 0.5 100 100.5 0 0.5 2003 2003.5 0 0.5 100000 100000.5 0 0.5 -1000000 -999999.5 ``` Any guidance is appreciate.
  7. Hi, I was having few questions regarding clock usage in tlm.These are as folllows:- 1.I wanted to know whether we can supply clock to initiator and target modules. 2.If it can be used ,then how to do we need need to connect to modules.Like instantiate clock in top module and how should we do port or named mapping ? If not,then why its not used ? Because i havent come across any examples in tlm which uses clocks. 3.If we are using blocking interface then using wait statement,just that data doesnot get overidden. And if its a case of nb_interface then we are using delay statements . My question here would be,can i create system clock input port and connect them ? I had tried but i had got a failed port mapping error message. Thanks & regards, Shubham
  8. I have been working on connection of two module having bi-directional ports, Is there any special signal required to connect two bi-directional ports? or anything else. Suggestions are welcome This is the error what I'm getting : Error: (E115) sc_signal<T> cannot have more than one driver: signal `Mila.signal_0' (sc_signal)first driver `Mila.Memory.port_4' (sc_inout)second driver `Mila.Alloc.port_3' (sc_inout)In file: ../../../../src/sysc/communication/sc_signal.cpp:73
  9. Hi, I assume its a basic question . Can someone please help me understand the basic flow of initiator and target by using a blocking interface in a c++ way. I had read the tutorial on doulous ,but i dint get the required explnation from my side. I do know the concepts of c++,but implementation wise i am bit on the slower side. It would be great if someone could explain it here through step wise. Thanks in advance. Ps: just for reference i am putting up the code.initiator.h,target.h,top.h,main.cpp Regards, Shubham
  10. Mat

    sensitivity list

    I have recently started learning SystemC and I have got an error with sensitivity list in "SC_METHOD". I am trying to implement a fifo and the error corresponds to following part of the code: SC_MODULE(fifo){ ... sc_int<8> rd_addr, wr_addr; ... void buffer_full(); ... SC_CTOR(fifo){ SC_METHOD(buffer_full); sensitive << rd_addr << wr_addr; } }; I get error when compiling the code and it complains about sensitivity list. I would appreciate if someone could let me know what is wrong with the sensitivity list. how should I make "buffer_full" process sensitive to the changes in rd_addr and wr_addr. I also tried following syntax to see if it works with single bit sensitivity but still no success sensitive << rd_addr[0]; Many thanks
  11. Hi, I was having few basic doubts regarding tlm,I am using system c again after few months. I wanted to know ,how exactly tlm is being used.I know the basics of system c and was approaching to start with tlm. I had googled to see few of tlm uses,but i was not able to catch up those points. I want to know under this scenario,like if i had modelled a system in system c and was having 5 files,design.cpp,producer.cpp,consumer.cpp,top.cpp,main.cpp .I would have used threads as function and called at particular time and would do the communicvation between modules.But what about tlm,as i had read in tlm we are having initiator and target and there are different types of interface connections which can be used for communication. But my question here would be,how and where would i put those 5 files when commuication mode being used is tlm.Do i need to model producer as initiator & vice versa & use any of the interface method of tlm or what !? Any help would be appreciated a lot. Thank you. Regards, Shubham
  12. shubham_v

    d flipflop output

    Hi, I have came back to system c after 6 months, again. I was trying to solve different basic examples of system c. The code is getting compiled,but i am not able to view the desired output. My output is not at all changing,i am not sure whether my function is getting hit or not. Please have a look at the code below and any help would b appreciated. In code,i have added stimulus first and then monitor to check wheteher my function was getting invoked.Again ,in main file also i passed the input. But from ,nowhere i am getting the output. Please help! https://www.edaplayground.com/x/5qEA Ps:Not only this example,the other examples such as combinational circuits,encoders,decoders. I am facing the same issue with respect to all of them.There must be a common mistake which i am repeating. Thanks & regards, shubham_v
  13. Lynn Garibaldi

    Call for Participation - IEEE P1666

    The IEEE P1666 (SystemC) Working Group is now operating and looking for new members. If your company is a Corporate IEEE member and you use SystemC for your business, think about joining the P1666 Working Group to make the SystemC standard even better. If you have any questions about joining P1666, please contact Jerome Cornet (jerome.cornet@st.com), IEEE SystemC WG Chair, and Jonathan Goldberg (goldberg.j@ieee.org), IEEE representative for SystemC.
  14. Hi, I am learning systemc/TLM2.0, I have a confusions in using the phases, When it comes to AT modeling, BEGIN_REQ and END_REQ are used to write data from initiator to target and BEGIN_RESP and END_RESP are use to read from traget to initiator OR we should split the write to target in 4 different phases and read from target in 4 different phases? I am aware of return path and early completion , i just want to have clearity on usage of request and response phases,
  15. Hi, above image is taken from LRM from section, During read command 1.is it 10ns in return path is for the target to perform read from target memory to data_pointer of initiator present in target as a part of generic payload member? if not than when is the actual read happens ? 2.what is target doing from 110ns to 150ns ? 3.how do i interpret 5ns present in return of BEGIN_RESP Please help . 
  16. let's assume there are two classes , A and B and in sc_main i am creating the object of A "only" and in class B i am using sc_find_object(hierarchical name of A) then the result from sc_find_object is sc_object type but class A is sc_module so, i typecast-ed into sc_module but still i am not able to call the Api's of class A inside class B. below code is just psedo code . sorry if there is any mistake . it is just for explaining the scenario. sc_main { A obj=new A("objectA"); } class A: sc_core:: sc_module { public: void fun() { cout<<"Hello world"; } }; class B { public: void function() { sc_core::sc_object* obj = sc_core::sc_find_object("objectA"); sc_core::sc_module* ObjNew ObjNew = dynamic_cast<sc_core::sc_module*> (obj); ObjNew->fun() - i.e fun exist in class B . but it is showing error } }; please help
  17. I am totally new to systemc. i am using gcc 7.3.0. while compiling it says error: std::gets has not been declared... while searching for a solution i found that gcc 4.8 is hugely compatible with c++11... so does i have to download gcc 4.8? any help will be hugely appreciated
  18. Philipp A Hartmann

    Support for C++11/14 in SystemC 2.3.2

    In the SystemC 2.3.2 review thread Ameya Vikram Singh (@AmeyaVS) reported the following observation: I'll open a separate topic to discuss the details.
  19. Hey everyone, As of now , i am reffering textbook "SYSTEM C-FROM THE GROUND UP". I wanted to have the solutions of example problems given in that book. Can anyone,please tell me where can i find them? I am not able to find solutions on the link provided in the textbook. Thanx in advance. Regards, Veeresh K
  20. In my code the variable 'inter' is changing its value by itself whenever, it is read/assigned. Please help void dff(){ cout<<"IN DFF"<<endl; cout<<sc_time_stamp()<<endl; wait(10,SC_NS); cout<<sc_time_stamp()<<endl; while(true){ wait(); cout<<"\nIN = "<<in.read()<<" TIME" <<sc_time_stamp()<<endl; inter.write(in.read()); cout<<"\nInter before wait= "<<inter.read()<<endl; wait(10,SC_NS); out.write(inter.read()); cout<<"\nInter after wait= "<<inter.read()<<endl; cout<<"\nOUT = "<<out.read()<<" TIME" <<sc_time_stamp()<<endl; cout<<"\nIN when outed = "<<in.read()<<endl; } } The Complete Code is at: here Please help. Once you run the progam, the value of inter 'before wait' and 'after wait' in the ouput. Thanks in advance
  21. Hi , I am trying to trace out the wave for the input and the output. I have tried for different ways,but not getting the desired results. One of the way was,i created 2 same signals with diff. name in testbench file and tried to trace ,but i was not successful in doing so. Any suggestions to do? Thank you. ? Ps:- I have attached the code through which m trying to trace.Plz,help me out with this.I have modified the code according to the errors,So thats the reason for using namespace sc::core while declaring fifo tracing input.I am posting full code along with the errors. /////////ERRORS///////////////////////////////////// testbench.cpp: In function 'int sc_main(int, char**)':testbench.cpp:16:18: error: no match for call to '(sc_core::sc_fifo<sc_dt::sc_int<32> >) (sc_core::sc_fifo_in<int>&)'testbench.cpp:17:19: error: no match for call to '(sc_core::sc_fifo<sc_dt::sc_int<32> >) (sc_core::sc_fifo_out<int>&)'testbench.cpp:21:29: error: no matching function for call to 'sc_trace(sc_core::sc_trace_file*&, sc_core::sc_fifo_in<int>&, const char [6])' ////////////////////CODE///////////////////////////// #ifndef EXAMPLE_H #define EXAMPLE_H using namespace sc_dt; typedef sc_int<32> sc_int32; SC_MODULE(example) sc_fifo<sc_int32> fifo; //producer thread void producer_thread(); //consumer thread void consumer_thread(); SC_CTOR(example) : fifo(2) { SC_THREAD(producer_thread); SC_THREAD(consumer_thread); }; }; #endif ///////////////////////////////////////// #include <systemc.h> #include "example.h" using namespace sc_dt; void example::producer_thread() { int unsigned number_of_accesses = 4; for (int i = 0; i < number_of_accesses; i++) { sc_int32 value(i); cout << "[" << sc_time_stamp() << "] writing to FIFO value: " << value << ", free: " << fifo.num_free() << endl; fifo.write(value); cout << "[" << sc_time_stamp() << "] wrote to FIFO value: " << value << endl; wait(1, SC_NS); } } //consumer thread void example::consumer_thread() { sc_int<32> value(0); for (;;) { wait(4, SC_NS); fifo.read(value); cout << "[" << sc_time_stamp() << "] read from FIFO value: " << value << endl; } } ////////////////////////////////////////////////MAIN.CPP//////////////////// #include "systemc.h" #include "example.h" using namespace sc_dt; int sc_main(int, char* []) { sc_core::sc_fifo_out<int> output1; sc_core::sc_fifo_in<int> input1; //create the instance of the example example eg1("example_inst"); eg1.fifo(input1); eg1.fifo(output1); sc_trace_file*tf=sc_create_vcd_trace_file("fi"); sc_trace(tf,input1,"input"); sc_trace(tf,output1,"output"); sc_start(); if(not sc_end_of_simulation_invoked()) { sc_stop; } sc_close_vcd_trace_file(tf); return 0; }
  22. veeresh k

    fifo waveform tracing

    Hey everyone, I am trying to trace out the wave for the input and the output. I have tried for different ways,but not getting the desired results. One of the way was,i created 2 same signals with diff. name in testbench file and tried to trace ,but i was not successful in doing so. Any suggestions to do? Thank you. ? Ps:- I have attached the code through which m trying to trace.Plz,help me out with this.I have modified the code according to the errors,So thats the reason for using namespace sc::core while declaring fifo tracing input. ///////////////////////////////////////////// using namespace sc_dt; int sc_main(int, char* []) { sc_core::sc_fifo_out<int> output1; sc_core::sc_fifo_in<int> input1; //create the instance of the example example eg1("example_inst"); eg1.fifo(input1); eg1.fifo(output1); sc_trace_file*tf=sc_create_vcd_trace_file("fi"); sc_trace(tf,input1,"input"); sc_trace(tf,output1,"output"); sc_start(); if(not sc_end_of_simulation_invoked()) { sc_stop; } sc_close_vcd_trace_file(tf); return 0; }
  23. veeresh k

    fifo example

    Hi. I have taken this example from a book and tried to execute it,But i got few errors. I have compared this code with std 2011 and made changes according to that like using namspace sc_core . I am not able to find a right solution for this one. Can someone plese help me out with this.I have posted the code below along with the error,check it out. Thank you. //error////////// In file included from testbench.cpp:6:0:head1.h: In member function 'void www::woperation()':head1.h:16:9: error: 'class sc_core::sc_port<sc_core::sc_fifo_out_if<int> >' has no member named 'write'In file included from testbench.cpp:7:0:head2.h: In member function 'void rrr::roperation()':head2.h:17:9: error: 'class sc_core::sc_port<sc_core::sc_fifo_in_if<int> >' has no member named 'read'  ////////code///// #include<systemc.h> #include"Head1.h" #include"Head2.h" int sc_main(int argc, char* argv[]) { sc_fifo<int> fifo(10); writer w("writer"); reader r("reader"); w.out(fifo); r.in(fifo); sc_start(-1); return 0; } //header1 #include<systemc.h> SC_MODULE(reader) { sc_port<sc_fifo_in_if<int> > in; void roperation() { int val; while (true) { wait(10, SC_NS) for (int i = 0; i <= 15; i++) { in.read(val); cout << val << endl; } } cout << "Availaible : " << in.num availaible() << endl; } SC_CTOR(writer) { SC_THREAD(woperation); } }; //header2 #include<systemc.h> SC_MODULE(writer) { sc_port<sc_fifo_out_if<int> > out; void woperation() { int val = 0; while (true) { wait(10, SC_NS); for (int i = 0; i <= 20; i++) { out.write(val++); } } } SC_CTOR(writer) { SC_THREAD(woperation); } };
  24. veeresh k

    system c beginner

    Hi, I am new to system c. I am trying to learn it step by step,but getting messed up with arrival of every new topic. Any suggestions for good book ? Currently i am studying system c primer by J.Bhasker. Please, help me out. Thank you.
  25. Hi, It seems I have hit a bug in VCD tracing implementation in SystemC release 2.3.2. Here is the bracktrace captured in GDB: (minimal example available here: https://github.com/AmeyaVS/SystemC_ramblings/tree/dev) as one can observe the exception: SIGFPE in systemc-2.3.2/src/sysc/tracing/sc_trace_file_base.cpp:268 due to divide by zero error. GNU gdb (Ubuntu 8.1-0ubuntu3) Copyright (C) 2018 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "x86_64-linux-gnu". Type "show configuration" for configuration details. For bug reporting instructions, please see: <http://www.gnu.org/software/gdb/bugs/>. Find the GDB manual and other documentation resources online at: <http://www.gnu.org/software/gdb/documentation/>. For help, type "help". Type "apropos word" to search for commands related to "word"... Reading symbols from /home/ameya/Documents/demo/SystemC_ramblings/src/02_adder/build/tests/AdderTest/AdderTest.run...done. (gdb) r Starting program: /home/ameya/Documents/demo/SystemC_ramblings/src/02_adder/build/tests/AdderTest/AdderTest.run [Thread debugging using libthread_db enabled] Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1". SystemC 2.3.2-Accellera --- May 1 2018 16:30:17 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED At time 0 s :: (a, b, cin): 100 (sum, carry_out): 00 At time 0 s :: (a, b, cin): 010 (sum, carry_out): 00 At time 0 s :: (a, b, cin): 110 (sum, carry_out): 10 At time 0 s :: (a, b, cin): 001 (sum, carry_out): 10 At time 0 s :: (a, b, cin): 101 (sum, carry_out): 11 At time 0 s :: (a, b, cin): 011 (sum, carry_out): 10 At time 0 s :: (a, b, cin): 111 (sum, carry_out): 00 At time 0 s :: (a, b, cin): 111 (sum, carry_out): 01 Info: /OSCI/SystemC: Simulation stopped by user. Program received signal SIGFPE, Arithmetic exception. 0x00007ffff7b57799 in sc_core::sc_trace_file_base::timestamp_in_trace_units (this=this@entry=0x5555557a3730, high=@0x7fffffffc658: 93824994651128, low=@0x7fffffffc660: 140737488346560) at /home/ameya/apps/src/systemc/systemc-2.3.2/src/sysc/tracing/sc_trace_file_base.cpp:268 268 unit_type unit_divisor = trace_unit_fs / kernel_unit_fs; (gdb) bt #0 0x00007ffff7b57799 in sc_core::sc_trace_file_base::timestamp_in_trace_units (this=this@entry=0x5555557a3730, high=@0x7fffffffc658: 93824994651128, low=@0x7fffffffc660: 140737488346560) at /home/ameya/apps/src/systemc/systemc-2.3.2/src/sysc/tracing/sc_trace_file_base.cpp:268 #1 0x00007ffff7b5d8a2 in sc_core::vcd_trace_file::get_time_stamp (this=this@entry=0x5555557a3730, now_units_high=@0x7fffffffc658: 93824994651128, now_units_low=@0x7fffffffc660: 140737488346560) at /home/ameya/apps/src/systemc/systemc-2.3.2/src/sysc/tracing/sc_vcd_trace.cpp:2086 #2 0x00007ffff7b5e242 in sc_core::vcd_trace_file::~vcd_trace_file (this=0x5555557a3730, __in_chrg=<optimized out>) at /home/ameya/apps/src/systemc/systemc-2.3.2/src/sysc/tracing/sc_vcd_trace.cpp:2145 #3 0x00007ffff7b5e319 in sc_core::vcd_trace_file::~vcd_trace_file (this=0x5555557a3730, __in_chrg=<optimized out>) at /home/ameya/apps/src/systemc/systemc-2.3.2/src/sysc/tracing/sc_vcd_trace.cpp:2153 #4 0x000055555555cfc1 in sc_main (argc=1, argv=0x5555557a2bf0) at /home/ameya/Documents/demo/SystemC_ramblings/src/02_adder/tests/AdderTest/src/full_adder_main.cpp:37 #5 0x00007ffff7b32e24 in sc_core::sc_elab_and_sim (argc=1, argv=<optimized out>) at /home/ameya/apps/src/systemc/systemc-2.3.2/src/sysc/kernel/sc_main_main.cpp:87 #6 0x00007ffff7097b97 in __libc_start_main (main=0x7ffff7aa1fa0 <main(int, char**)>, argc=1, argv=0x7fffffffddb8, init=<optimized out>, fini=<optimized out>, rtld_fini=<optimized out>, stack_end=0x7fffffffdda8) at ../csu/libc-start.c:310 #7 0x000055555555c08a in _start () (gdb) I seems to happen only when the simulation time is not progressing. One can apply the below patch to branch (dev) available under here for the following sub-directory: https://github.com/AmeyaVS/SystemC_ramblings/tree/dev/src/02_adder diff --git a/src/02_adder/tests/AdderTest/src/driver.cpp b/src/02_adder/tests/AdderTest/src/driver.cpp index e70aea1..26169b7 100644 --- a/src/02_adder/tests/AdderTest/src/driver.cpp +++ b/src/02_adder/tests/AdderTest/src/driver.cpp @@ -7,8 +7,14 @@ void driver::prc_driver() { d_a = pattern[0]; d_b = pattern[1]; d_cin = pattern[2]; - wait(5, sc_core::SC_NS); + //wait(5, sc_core::SC_NS); + wait(sc_core::SC_ZERO_TIME); pattern++; + if (pattern == 0) { + break; + } } + wait(sc_core::SC_ZERO_TIME); + sc_core::sc_stop(); } This behavior is not reproduced in SystemC release 2.3.1a. I will try to debug further and hopefully with probable fix. Regards, Ameya Vikram Singh