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Found 105 results

  1. // MODULE 1 WRITING THE OUT1 to Value 1 SC_MODULE(MODULE_1){ public: //-------------PORTS DECLARATIONS--------------------------- sc_in<bool> reset; sc_out<bool> out1 ; // ---event sc_event sig_written; public: void Process(); public: SC_CTOR(MODULE_1){ SC_METHOD(Process); sensitive << reset; } void Process() { if (reset == 1) out1.write(1); sig_written.notify(); // to make it runnable within the execution phase and not in the Next delta cycle } }; //---------------------------------------------------------------------------------------------------------- // MODULE 2 READING OUTPUT VALUE FROM MODULE_1 SC_MODULE(MODULE_2){ public: //-------------PORTS DECLARATIONS--------------------------- sc_in<bool> input1; sc_out<bool> out2 ; public: // HOW TO DEFINE EVENT HERE ? // PROCESS void Process(); public: SC_CTOR(MODULE_2){ SC_METHOD(Process); sensitive << input1; } void Process() { bool x; x = input1.read(); // reading the Output Value from Module 1. I want to read here 1 because of output // written in the MODULE_1 is 1 if (x == 1) out2.write(1); // HOW TO USE EVENT HERE ? SHARED EVENT } }; Hi I am outputting One value from MODULE 1 and notifying it through sig_written.notify() event to make it detectable in the same execution phase and not in the next delta cycle. Can You tell me How to use the event in the MODULE_2 to detect this event and read the value immediately without going into next delta cycle. thanks
  2. Hi I have 3 to 4 modules and they have 3 to 4 inputs but to synchronize the timing of inputs as they all have to have specific value only then my THREAD PROCESS should run, I am using value_changed_event inside the THREAD PROCESS of the MODULE by using wait(sig.value_changed_event()). But In some MODULES, I am initializing large arrays and due to this when the value changes then it rerun from the 1st Module to the Last and stops in the mid-way displaying the stack over flow as the exception. What Should be the possible solution for this ? I have Increase the Stack size upto 1Giga but still does not work. Thanks
  3. Hi In TLM, I am connecting two modules with the Initiator socket and target socket. My question is that "Is that possible to have also signal based connection between the modules as well as the Socket based connection " ? Can we have communication in both ways in SystemC ? Thanks
  4. Memory Allocation In SystemC

    Hi, I have to Allocate Memory for my data in SystemC. We Use malloc in C Language and New in C++ to dynamically Allocate Memory. But today I have read that we cannot use New and Delete Operators in System C as they are not synthesizeable. Which command should I use for Memory Allocation in System C. Thanks.
  5. SystemC for Hardware Design

    Hi, We use SystemC to define specific Hardware Blocks like Memory, Caches and Bus etc. We define Header and CPP files and Include processes to define the functionalities being done by each module. BUT let's say Now we have to define the general settings of the Whole Network (like NEURAL NETWORKS AND DEEP LEARNING NETWORKS) which include Two or three STRUCTS about configuration and we make additional Header and CPP file for this. WILL THAT BE CONSIDER AS A FURTHER HARDWARE IN THE SYSTEM C Design. Is that allowed or not ? This is a general question? Please explain me this in detail? Thanks
  6. hi, I want to implement systemC TLM design that uses a simple bus to communicate between the two separate modules. I want to know how to use systemc built in simple bus library. Please help me in this regard. Thanks in advance.
  7. hi, I want to implement systemC TLM design that uses a simple bus to communicate between the two separate modules. I want to know how to use systemc built in simple bus. Please help me in this regard. Thanks in advance.
  8. void Wcache0::getAddrForSingleWeight(const channel_t co, kernel_t kernel_1, const weightaddr_t ci_offset, PEID_t &PEID, blockID_t &blockID, rowID_t &rowID, weightID_t &weightID) Hi, Can we pass arguments inside the process in SystemC. If Yes then how we have to register the process in the constructor? Thanks . Below is the MODULE Wcache0 and I am trying to write getAddrForSingleWeight process which will be called inside another process which is register as SC_THREAD.
  9. Hi, Can we pass arguments inside the process in SystemC. If Yes then how we have to register the process in the constructor? Thanks . Below is the MODULE Wcache0 and I am trying to write getAddrForSingleWeight process which will be called inside another process which is register as SC_THREAD. void Wcache0::getAddrForSingleWeight(const channel_t co, kernel_t kernel_1, const weightaddr_t ci_offset, PEID_t &PEID, blockID_t &blockID, rowID_t &rowID, weightID_t &weightID)
  10. Hi I have written a sample code in SystemC. I am defining some typedefs and global variable outside SC_MODULE. Is that fine? and plus I am also defining the member function as static. Please correct my code. Thanks
  11. Hi. I am working on the Design Flow of the Given Architecture and I making the SystemC Model on the basis of the given diagram description. I not included in my System C Model the shared DRAM. Can You guide me How I have to model the Shared DRAM near Memory Controller Box in System C (As a Module or not ?) as shown in the first picture. Give me some System C Block diagram for this architecture as I am new to the System C. Thanks
  12. Saw the UVM-SystemC-1.0-beta1 download link, try to install it, but according to the INSTALL file, I can't find "configure" in the package. How could I install it?
  13. clock problem

    Hi all, i'm implementing a timer/counter(8-bit) that should not increment on every clock and i'm not supposed to provide any input clock port . But i need clock period in my design so my question is " How would i provide clock period(through constructor)?" here is the link to my working code on EDAplayground : http://www.edaplayground.com/x/4_dY if there is any problem in my code please feel free to tell me. regards, jatin
  14. Hi all, is there any way to implement the intra assignment delay in systemC without using sc_event()? for example : in verilog we write out = #10 in1 + in2; // intra assignment delay. how would i implement the same in systemC? regards, jatin
  15. Hello, I am using SystemC 2.3.0. I am wondering how I can profile the SystemC library. I found we can use options like "--enable-debug" and "--disable-optimize" for debugging and optimization, respectively, but I was unable to find such an option to enable profiling. I need to use gprof and pass "-pg" options when building SystemC. Any help is greatly appreciated! Thank you in advance.
  16. I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals. I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish. So would someone let me know what's the right way to handle the clock and reset signals?
  17. Hey, Kahn Process Networks are defined by the usage of unbounded FIFOs with blocking reads and non-blocking writes. I read on several sources that KPN with bounded FIFO size (i.e. blocking read and blocking write) can be implemented with SystemC (e.g. Grötker et al). It seams that the event based scheduler in SystemC behaves different like data-driven scheduler or a demand-driven for KPNs. I simulated the networks of Park's Dissertation shown on page 36 and 42 which should end up in an artificial deadlock (deadlock which occurs because of blocking write). A global artificial deadlock in SystemC would result in no scheduled events, and therefore, the simulation should be stopped. However, even with buffer size 1 for all FIFOs both examples from Park are continuing with execution: Page 63: http://www.edaplayground.com/x/6Mfi Page 42: http://www.edaplayground.com/x/4jLZ Note that edaplayground exits because of to much output. If you want to test it you better download it and run it on your PC. Apparently, the SystemC scheduler finds automatically a schedule for the KPN such that no artificial deadlocks occur. My question: is there an example where I could also see an artificial deadlock in SystemC? Thanks and Regards Matthias
  18. Hi, I am getting the same sequence of random numbers every time I run my SystemC code ... there is too much code to post here, so I will attempt to describe what I am doing ... I have written a DUT (SC_MODULE) with 9 input ports and I have written a Driver (SC_MODULE) to drive one of those ports, I have instantiated 9 Drivers and 1 DUT in sc_main ... the Driver uses rand() ... Each Driver produces the exact same sequence of random numbers ... I didn't some looking on the C++ forums and tried the following ... 1. Adding srand(time(NULL)) to the Driver ... but it won't compile 2. Adding srand(time(NULL)) to just sc_main ... compiled ok but made no difference 3. Adding srand(time(NULL)) to the constructor, I added it to the Driver SC_CTOR ... compiled ok but again made no difference Those were the only possible solutions I found on the C++ forums ... I didn't see anything related on here ... As always any and all help would be greatly appreciated :-)
  19. I am a novice at SystemC (some OOP background but not much) ... I am getting an error for the code below ... ../src/xor2.h:20:31: error: invalid initializer for array member 'nand<2> xor2::nand2 [4]' I have much more complicated but netted my problem down to this much simpler and smaller example ... #include "systemc.h" template <int width> SC_MODULE(nand) { sc_in<bool> A[width]; sc_out<bool> F; void nand_func() { F.write(!and_reduce(A)); } SC_CTOR(nand) { SC_METHOD(nand_func); sensitive << A; } }; #include "systemc.h" #include "nand.h" SC_MODULE(xor2) { sc_in<bool> A, B; sc_out<bool> F; nand<2> nand2[4]; sc_signal<bool> sig1, sig2, sig3; SC_CTOR(xor2) : nand2("NAND2") { nand2[0].A[0](A); nand2[0].A[1](B); nand2[0].F(sig1); nand2[1].A[0](A); nand2[1].A[1](sig1); nand2[1].F(sig2); nand2[2].A[0](sig1); nand2[2].A[1](B); nand2[2].F(sig3); nand2[3].A[0](sig2); nand2[3].A[1](sig3); nand2[3].F(F); } }; I would greatly appreciate any help and suggestions of ways to use multiple template'd modules in this way ... xor2.h nand.h
  20. Hi everyone, my initiator is writing to a specific register but I want to block the initiator if a certain bit of the target register is set (1). is there a way to do that?
  21. Hello, Is there a way to generate execution trace for a SystemC project? Thanks, R.Adiga
  22. Hello All, I am working on SystemC-UVM based testbench. I have created UVM based testbench using UVM code generator. Here I am using three different agents in UVM generator which I have defined as a part of the configuration file which was further being provided to UVM code generator to generate test bench skeleton. And here, in of the agent driver, the code snippet is as: // Drive the inputs of the DUT UVM_INFO(this->name(),"Driving transaction:",0); req.print(); // TODO put your code here But when I try to read the value in my test-case, then I see an error as: And this error is observed inside print() function, once I comment the line "req.print()" from the above snippet the error is no more observed and my test-case runs fine.
  23. Hello There is an existing model with tlm1.0 sockets - sc_port and sc_export. Is it possible to bind these sockets to tlm2.0 initiator and target sockets? If yes, then what is the conversion procedure involved? I'm new to SystemC, any help/insight on this is appreciated. Thanks.
  24. Hello, I'm just starting off with TLM-2.0 and would like to explore more about the use cases for byte_enable_ptr. In TLM manual, I see that " A value of 0 shall indicate that that corresponding byte is disabled, and a value of 0xff shall indicate that the corresponding byte is enabled"; Does this mean that we can switch between 0xff and 0x0 if required for every transaction? TLM manual also states that Byte Enable can be used to create burst transfers, can anyone please explain this? Thanks, R.Adiga
  25. Folks, I have requirement to calculate bandwidth per socket. This means I need to count how many transactions were sent on a given socket, and also pass clock information. Are there any example of customizing socket where I can calculate these things and print of at the end of the simulations.
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