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Found 5 results

  1. veeresh k

    clock generation in system c

    Hi, I have came across this counter example from other website. Can u please tell me ,where have we intitialised the main clock. I know the default time period is 1ps,but i am not getting the start of the clock is from which point. I am not knowing the reason for its generation in waveform viewer. Thank you. Below is the code: #include "systemc.h" #include "design.cpp" int sc_main (int argc, char* argv[]) { sc_signal<bool> clock; sc_signal<bool> reset; sc_signal<bool> enable; sc_signal<sc_uint<4> > counter_out; int i = 0; // Connect the DUT first_counter counter("COUNTER"); counter.clock(clock); counter.reset(reset); counter.enable(enable); counter.counter_out(counter_out); sc_start(1, SC_NS); // Open VCD file sc_trace_file *wf = sc_create_vcd_trace_file("counter"); // Dump the desired signals sc_trace(wf, clock, "clock"); sc_trace(wf, reset, "reset"); sc_trace(wf, enable, "enable"); sc_trace(wf, counter_out, "count"); // Initialize all variables reset = 0; // initial value of reset enable = 0; // initial value of enable for (i=0;i<5;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } reset = 1; // Assert the reset cout << "@" << sc_time_stamp() <<" Asserting reset\n" << endl; for (i=0;i<10;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } reset = 0; // De-assert the reset cout << "@" << sc_time_stamp() <<" De-Asserting reset\n" << endl; for (i=0;i<5;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } cout << "@" << sc_time_stamp() <<" Asserting Enable\n" << endl; enable = 1; // Assert enable for (i=0;i<20;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } cout << "@" << sc_time_stamp() <<" De-Asserting Enable\n" << endl; enable = 0; // De-assert enable cout << "@" << sc_time_stamp() <<" Terminating simulation\n" << endl; sc_close_vcd_trace_file(wf); return 0;// Terminate simulation }
  2. Dear Sir, I am getting the following errors in running this program: error C2466: cannot allocate an array of constant size 0 error C2133: 'matrix' : unknown size Assume I am getting m and n through functions already written and declared in constructor. SC_MODULE(sc_fifo_array) { public: SC_HAS_PROCESS(sc_fifo_array); sc_fifo_array(sc_module_name name_):sc_module(name_) { int m,n; int *matrix[m]; for (int i=0; i<m; i++) matrix=new int[n]; matrix[0][0]=20; cout<<"\nmatrix="<<matrix[0][0]<<"\n"; } public: int m,n; }; Does system C does not support variable size matrix?
  3. Uzmeed

    Errors in code

    Hi Attached is the code for parallel to serial and serial to parallel conversion i have two problems in converter.cpp 1- count is not incrementing the value 2- Lout is not getting value of PS_reg in SPPS48 i am getting the following error ./../../SPPS48.h: In constructor 'SPPS48::SPPS48(sc_core::sc_module_name)': ../../../SPPS48.h:51:9: error: 'struct SPPS48' has no member named 'M1' ../../../SPPS48.h:51:16: error: expected type-specifier before 'SPPS' ../../../SPPS48.h:51:16: error: expected ';' before 'SPPS' ../../../SPPS48.h:52:3: error: 'M1' was not declared in this scope ../../../SPPS48.h:60:3: error: 'M2' was not declared in this scope ../../../SPPS48.h:60:10: error: expected type-specifier before 'SPPS' ../../../SPPS48.h:60:10: error: expected ';' before 'SPPS' ../../../SPPS48.h:69:3: error: 'M3' was not declared in this scope ../../../SPPS48.h:69:10: error: expected type-specifier before 'SPPS' ../../../SPPS48.h:69:10: error: expected ';' before 'SPPS' convert.cpp main.cpp SPPS.h SPPS48.h
  4. wasim6691

    Reading a binary File

    Hello I wand to read the binary file in System C. Can I use the malloc() function as we used in C to store the content of the file in some buffer. Thanks. The fread() command is used in System C or there is some other command in System C.
  5. hai to all Iam karthik,doing my masters in VLSI DESIGN ,i found my interest in system level design and i wish to do project in systemcTLM based simulation.As a starter ,learning systemC language and i want to learn how systemc TLM differ by verilog,VHDL and other languages by results.i.e by simulation...kindly guide me regarding by suggesting some projects or papers in these domains.. keywords:co-simulation,systemc based simulations..
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