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Found 2 results

  1. I have recently started using SystemC for my project. I would appreciate if someone could help me with following problem. How can I select part of input port in SystemC? In Verilog it can be done easily by choosing the required bits, e.g., inputPort[3:1] How can I do this in Systemc? I have defined an input port as follows sc_in < sc_int<5> > inputPort; What is the syntax to read bits e.g., [1:3] from inputPort like I did in Verilog? I tried few syntax like inputPort.read({1:3}) but no success.
  2. Previous versions of IPXACT has attributes, 'left' and 'right' inside internalPortReference element of adHocConnection in design IPXACT as shown in the following 4 lines of xml. <spirit:adHocConnection> <spirit:name>....</spirit:name> <spirit:internalPortReference spirit:ComponentRef = "..." spirit:PortRef=".." spirit:left="..." spirit:right="...."/> </spirit:adHocConnection> These attributes basically say that which vector range of port from one component is mapped to another (I assume) However, the same IPXACT with latest schema, while validation gives schema error stating, attribute right/left is not allowed. Even the latest xsd files available with accellera doesn't define these attributes.There must be some means how currently, these multibit adHocConnections are mapped between two components inside an IPXACT-design. What could be the solution for this?
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