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ljepson74 posted a topic in UVM SystemVerilog DiscussionsA backslash can be used to extend a string literal onto the next line if "the new line is immediately preceded by a \ (backslash)." Section 5.9 of 1800-2012.pdf, the SystemVerilog LRM I don't think I have ever been able to get this work and w/o looking I seem to recall it has been in Verilog/SystemVerilog for a while. Can someone tell me if vendors support this and perhaps correct the code below on edaplayground? example from LRM: $display("Humpty Dumpty sat on a wall. \ Humpty Dumpty had a great fall."); See example here (on Sept 29, urls below are updated in response to Tudor comment below. thx.): http://www.edaplayground.com/x/4Tyw https://www.edaplayground.com/x/4Tyw //if the above does not work, try this one, with https://