Search the Community

Showing results for tags 'simulation'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Synthesizable Subset v1.4 Public Review
    • SystemC Verification (UVM-SystemC, SCV)
  • UVM (Universal Verification Methodology)
    • UVM 1.2 Public Review
    • Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • Simulator Specific Issues
    • UVM Commercial Announcements
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • OCP (Open Core Protocol)
  • UCIS (Unified Coverage Interoperability Standard)
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption


  • Community Calendar

Found 5 results

  1. In my project there are several functions which perform SystemC simulations (each has its own declaration prelude and sc_start()). So they are constructed as follows: // first Simulation: sc_signal<double> s1_sim1; .. ControlFoo<double> *cf = new ControlFoo<double>(); cf->Foo_port(s1_sim1); .. sc_start(); // works fine delete(cf); .. // second Simulation: sc_signal<double> s1_sim2; // this leads to an exception The first simulation runs as desired until the sc_stop(). But when I try to declare new sc_signals after the first simulation is completed then it comes to an exception. How do I solve my problem? Best regards Anne (I also asked this on stackoverflow but no response yet.
  2. Hi, Recently I used the following Verilog code in my project: module dff8( input wire CLK, input wire RST, input wire [7:0] D0, output reg [7:0] Q0 ); always @( posedge CLK or negedge RST ) begin if ( RST == 1'b0 ) begin Q0 <= 8'b0; end else begin Q0 <= #10 D0; end end endmodule Is there any way how to model #<DELAY> in SystemC. The example of systemc register that I use is below. SC_MODULE(dff8) { // port declarations sc_in<bool> CLK; sc_in<bool> RST; sc_in<sc_uint<8> > D0; sc_out<sc_uint<8> > Q0; // process declaration void do_dff8() { if ( == 0) { Q0.write(0); } else { // HOW TO ADD DELAY HERE? Q0.write(; } } SC_HAS_PROCESS(dff8); dff8(sc_module_name inst) : sc_module(inst) { SC_METHOD(do_dff8); sensitive << CLK.pos(); sensitive << RST.neg(); } }; Thanks for any help.
  3. Hello, I used b_transport in of my TL models to exchange data from a transactor to a memory. It was a read/write/reset operation kinda thing. Data from memory is transferred to another module attached to the transactor. What I noticed was at the end of my b_transport call, the simulation ends directly, without returning to the transactor thread in order to affect the obtained data from memory (in case of a read operation, for example) to the port connecting the transactor and the other module. Why is this? Code for reference: memory // TLM-2 blocking transport method virtual void b_transport(tlm::tlm_generic_payload& trans, sc_time& delay) { /** Code here to transfer data **/ // Realize wait delay to advance simulation time wait(delay); // After wait, the simulator goes directly back to sc_main } transactor void thread_process() { /** Code here **/ while(true) { wait(CLK->posedge_event()); // Wait on CLK posedge event /** More code here **/ payload_setup(trans, cmd, data_ref, addr); rtt2a_socket->b_transport(*trans, delay); // Blocking transport call. Trans is a generic payload // I expected the program to return here, but it didn't // Initiator obliged to check response status and delay if (trans->is_response_error()) SC_REPORT_ERROR("TLM-2", "Response error from b_transport"); if(cmd == tlm::TLM_READ_COMMAND) DATA->write(d_word_t(data)); // Write data back to port. So far, this does not work properly } Thank you,
  4. Good day, I have a question regarding how to determine the appropriate delay value for the wait( ) function call. In the target b_transport callback, we can add delay to the simulation time by passing delay amount to the wait( ) function. In simulation that uses quantum and temporal decoupling that targets super fast instruction accurate simulation, the timing does not have to be very detail (loosely timed). With or without delay in the target callback function will not cause any functional inaccuracy and still we could produce the platform that can support firmware/software development. Still if we want to put a delay to the wait( ), how can we determine the appropriate delay value for the function parameter? Thank you. Regards, Arya.
  5. Hi everybody, I have a simple question (not so sure if the answer is simple too). Is it possible to "pause"/"halt" the simulation temporarily? It would be useful for me in two scenarios: Whenever the simulation reaches a specified point in the code. Just like a breakpoint, but not having the need to use a debugger. So whenever the user presses a key, the simulation goes on. Whenever the simulation reaches a point, where a user needs to send an input. It is similar to the previous one, but the here the user would need to enter an input (int, double, string, etc.). I understand that this may be harder for the simulation. So, any ideas? Is there any sc_pause? I know that there is a sc_halt, but it looks like it works only with threads, which would not be suitable to be called from an AMS module. Thanks a lot! ;-)