Jump to content

Search the Community

Showing results for tags 'sequence'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI Public Review
  • UVM (Universal Verification Methodology)
    • Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus Discussion
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • OCP (Open Core Protocol)
  • UCIS (Unified Coverage Interoperability Standard)
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Calendars

  • Community Calendar

Found 12 results

  1. Hi All, I have a sequence sending a created and randomized item using `uvm_send. The driver receives an item using try_next_item. Upon receiving, it drives the item and calls item_done. Using debug message after item_done, I can clearly see that item_done is called and returned but `uvm_send in sequence is still blocked and not doing forward to send next item (it implements a loop). Can anyone help me with possible reasons why `uvm_send would not return even when driver has called item_done and come out of item_done. Thanks in advance! Ninad
  2. Hi All, I have a scenario where i need to send n random bytes and out of n bytes i should able to corrupt few selected bytes. I have used Queue for selecting error bytes list. Transaction : rand bit [7:0] tx_data_byte[`MAX_DATA:0] ; // data byte array rand int unsigned tx_no_of_bytes_to_send ; // number of data bytes to send rand byte tx_err_bytes[$] ; //queue contains byte positions to be corrupted Example : consider i am sending 5 data bytes and I have to corrupt 2,4,5 bytes (corrupting data bytes is handled in driver) Sequence : `uvm_do_with( req, { tx_data_byte[0]=='h00; tx_data_byte[1]=='h11; tx_data_byte[2]=='h00; tx_data_byte[3]=='h99; tx_data_byte[4]=='h55; ///----------------- tx_no_of_bytes_to_send ==20; tx_err_bytes == {4,5,7}; }) I am seeing below error from the cadence simulator. Can somebody help me out in resolving this error . Error: Randomization constraint has error, which will cause the randomize function to return 0 and no new rand values will be set: This feature is currently not supported for queues, dynamic arrays, strings and associative arrays. Thank you
  3. *, Is one of these ways to have a sequence wait on an event preferred? If so, why? The following are code snippets from inside a sequence. 1) Create transaction and engage w/ driver, then wait for event. `uvm_create(req) start_item(req); m_state.wait_on_smthg(); // <--- wait here 2) Wait for event, then proceed m_state.wait_on_smthg(); // <--- wait here `uvm_create(req) start_item(req); In this case, the event being waited for is that data of a certain type is available.
  4. I am trying to synchronize when sequences are sent to the DUT. I send one transaction to the DUT at the beginning, and then I need to wait for the DUT to send out a transaction (much later) before I continue with my sequence. Right off the top, I was thinking I would add an analysis_imp, and when the DUT sends the transaction, have the agent broadcast it, and my sequence could trigger an event in say, the write function. I don't believe this makes sense though, as I don't believe ports were meant to be created in transient types, like a uvm_sequence. It appears as the only real "connection" the sequence has with the environment is through an agents sequencer. What would be ideal is if my sequence were simply waiting on an event that is triggered by receiving a transaction in an agent attached to the DUT, but i don't know where that event would live. Here is the body method of my "directed_test" sequence: start_item (txn, -1, a_sequencer); finish_item(txn); `uvm_info(report_id, "waiting for DUT to send an ARP reply...", UVM_LOW) <------- need something here to wait/sync to the DUT response `uvm_info(report_id, "OK to start next sequence item!", UVM_LOW) start_item (next_txn, -1, a_sequencer); finish_item(next_txn);
  5. In the body of a virtual sequence I have a sequence running inside fork join, which is then killed by disabling the thread, like so: virtual task body(); .... fork:seq_thread `uvm_do_on(my_seq, my_seqr) join @(negedge reset_b ); disable seq_thread; ... ... endtask; On doing this, we get the following error from the sequencer: [sEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.my_seqr' for sequence 'uvm_test_top.env.soc_v_sequencer.my_vseq.my_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues. What can I do in my virtual sequence to cleanly kill 'my_seq' when reset_b is asserted ?
  6. Following is the sequence code class basic_sequence extends from uvm_sequence(#sequence_item); sequence_item item; task body() fp1 =fscanf("abc.txt", addr, data); `uvm_do_with(item,{ item.addr = addr; item.data = data; }); endtask endclass I have constrained addr and data from file reading data. It is not happening with the above code. data_item is getting a random value. I have written a user-defined task to solve this problem like below task do_rw(int addr, int data); begin item = sequence_item::type_id::create("item",,get_full_name()); item.wr_adr.rand_mode(0); item.wr_dat.rand_mode(0); item.wr_adr = addr; item.wr_dat = data; start_item(item); randomize(if_item); finish_item(item); end endtask inplace of uvm_do_with call uder defined do_rw task like below fp1 = fscanf("abc.txt", addr, data); while(!eof(fp1) { do_rw(addr, data); } This will work. I used above solution to work. I really don't understand why uvm is not supporting it with uvm_do_with. any answers for fit?? Thanks, Satya
  7. Following is the example class my_sequence extends uvm_sequence... string file_name; `uvm_object_utils_begin(mysequence) `uvm_field_string(file_name,UVM_DEFAULT) `uvm_object_utils_end endclass class basic_test extends from uvm_test function build_phase(..) set_config_string("*", "file_name", abc.txt); endfunction endclass.. I am passing file_name(abc.txt) from test with set_config_string, but, it is not taking effect. I did the same thing in driver. it worked well. does UVM supports, overriding local variables in sequence. Please let me know... Thanks, Satya
  8. I am learning UVM. So far I was able to create the following environment for my DUT. Agents with monitors, drivers and sequences for all of the input-output interfaces from my DUT. A top level UVM env. Sequences to send valid data to DUT. I yet to implement scoreboard. I'm having some trouble to understand how to handle scenarios like following: For one of my tb->dut interfaces, TB needs to wait for an event (or transaction) from DUT. Once it receives the transaction from DUT, TB needs to send back a response. What is the best way to implement this? How can I monitor DUT transaction from sequence? I assume I need to wait for an event or something similar which will tell me that DUT has a new valid output in its interface. My agents have monitors which will monitor any new output signals from DUT. So, do I need to somehow bring this data from agent's monitor to my test/sequence class? I know that monitor has an analysis port and it can be used to send received data to scoreboard for checking. So, do I need to use the same port to read DUT output data, create valid response and send it to DUT? Thanks!
  9. `uvm_do_with(m_top_seq, {m_sub_seq.num_of_trans == 0;}) The above example results in a runtime null object failure for m_sub_seq Is there a way to overcome this without copying all m_sub_seq random variables to m_top_seq ?
  10. I've run into the following issue using the built-in UVM register tests. The built-in UVM register tests (seem to) start R/W-ing immediately after top-level reset is released. This was fine, initially. See attached image "Capture". We now have some delay between the release of top-level reset and the actual reset going to the register block. This is resulting in a read occurring before reset to the rtl regblock is released, and causes the test to hang. See attached image "Capture2". Without modifying the built-in register tests/sequences, how would anyone suggest that we cleanly delay the stimulus? Perhaps I just need to make the stimulus aware of the different reset when the model/stimulus is generated, or simple add some delay to a phase before the R/W-ing starts. (The former sounds right. If that's the solution, I'll need to figure out how we're generating the model/stimulus.) I've just started hunting around for the built-in UVM register test sequences and will return to it tomorrow, but will anyone tip me off as to what names I should be searching for? thanks This has been useful, https://verificationacademy.com/cookbook/registers/builtinsequences, but it seems I need to do some more reading and hunting before I grasp how the built-in register stimulus is created and used.
  11. Hello Everyone, I am trying to control a sub virtual sequencer's non-virtual sub sequencers using a top level virtual sequencer. It looks like this diagram. <start of diagram> .------------------------------------------------------. | my_test | .--------------------------------------------------. | | | sequences | | | '--------------------------------------------------' | | .--------------------------------------------------. | | | my_env | | | '--------------------------------------------------' | '/----------------------------------------------------\' / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ / \ .----------------------------------------------------------------------------------------------------. | my_env | | .------------------------. | | | my_virtual_sequencer | | | '------------------------' | | .-----------------------------------. .----------------------------. .---------------------------. | | | sub_virtual_agent | | sub_agent_a | | sub_agent_b | | | | .-------------------------------. | | .------------------------. | | .-----------------------. | | | | | sub_virtual_sequencer | | | | sub_sequencer_a | | | | sub_sequencer_b | | | | | '-------------------------------' | | '------------------------' | | '-----------------------' | | | | .-------------------------. | | .------------------------. | | .-----------------------. | | | | | sub_agent_3 | | | | driver_a | | | | driver_b | | | | | .-------------------------. | | | '------------------------' | | '-----------------------' | | | | | sub_agent_2 | | | | .------------------------. | | .-----------------------. | | | | .---------------------------. | | | | | monitor_a | | | | monitor_b | | | | | | sub_agent_1 | | | | | '------------------------' | | '-----------------------' | | | | | .-----------------------. | | | | '----------------------------' '---------------------------' | | | | | sub_sequencer_1 | | | | | | | | | '-----------------------' | | | | | | | | .-----------------------. | | | | | | | | | driver_1 | | | | | | | | | '-----------------------' | | | | | | | | .-----------------------. | | | | | | | | | monitor_1 | | |-' | | | | | '-----------------------' |-' | | | | '---------------------------' | | | '-----------------------------------' | '----------------------------------------------------------------------------------------------------' <end of diagram> I am trying to apply section 4.8 Virtual Sequences of uvm users guide. But I think I am missing on something. I have a top level virtual sequence that has the top level virtual sequencer as its p_sequencer. I have this in the macro: `uvm_declare_p_sequencer(my_virtual_sequencer) And then I have this in the task body() to access the sub sequencer of the sub virtual sequencer: `uvm_do_on(sub_sequence_1, p_sequencer.i_sub_virtual_sequencer.i_sub_sequencer_1); sub_sequence_1 is a physical sequence. Is this correct under the UVM standard? If not, how do I properly control i_sub_sequencer_1? This is how I access it in the test build_phase: uvm_config_db #(uvm_object_wrapper)::set(this, "i_my_env,i_my_virtual_sequencer.main_phase","default_sequence",my_virtual_sequence::type_id::get()); Any help/inputs to this is much appreciated. Thanks, Martin
  12. When a driver returns a response to the sequence, it calls 'set_id_info()' to set the identifiers of the transactions returned. This way, the originating sequence can correlate the response and the originating transaction, by matching the 2 fields sequence_id and transaction_id. This has a couple of drawbacks : the sequence writer must set this field 'transaction_id' by hand the transanction_id may not be unique - a bug can be introduced (sequence/driver) and go unnnoticed when the wrong matching occurs - worst scenario is when a user simply forgets to set it, and the matching still occurs, but is wrong ! An improvement/fix to address these 2 issues would be to use field 'inst_id' (which is unique) instead of 'transaction_id' (user defined). It looks to me the original intention was to use this field rather than 'transaction_id'. The code change would be : function void set_id_info(uvm_sequence_item item); if (item == null) begin uvm_report_fatal(get_full_name(), "set_id_info called with null parameter", UVM_NONE); end /* this.set_transaction_id(item.get_transaction_id()); */ this.set_transaction_id(item.get_inst_id()); this.set_sequence_id(item.get_sequence_id()); endfunction
×