Search the Community
Showing results for tags 'sensitive clk.pos()'.
Found 1 result
Hello All , I am a beginner in SystemC with Hardware verification background (sv/uvm). I coded a simple synchronous design (sensitive_pos (clk)) and ran the simulation using questasim10.2 . Sadly In waveform the behavior looked as a combination logic rather than a sequential one. Whether its the problem of simulator or systemc ? .Also what will be the best simulator for SystemC. Thanks in advance, Kavinkumar (MTS , AtriaLogic).