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Found 3 results

  1. Hello everybody, I would like to know if AMS and SystemC have two different schedulers. If yes then how do they interact? Moreover i would like to ask how many extensions does SystemC has? Thanks in advance
  2. Hi, I encounter a problem when using the sc_spawn primitive. THE SCENARIO is the following: I call sc_spawn each time a new request arrives on my component. Then, the request is handled by its own thread process, which leads to activate an edge in the FSM. The spawned process does not contain an infinite loop and terminate as soon as it finishes processing the request. THE PROBLEM: An unknown exception is thrown when the spawned thread process terminates. The exception comes from sc_core::sc_cor_pkg_qt::abort( ... ) apparently. Could any one help me or give me advice for solving this problem ? Best, Julien.
  3. Hi everybody, I have a question regarding wait(SC_ZERO_TIME) statements. I am working on a virtual platform for embedded systems with several ISSs, interconnections and memory modules. The memory thread has to be triggered on the positive edge of the request signal and keep on serving subsequent requests if the signal is kept high by the initiator after the first request. The code below shows the memory module implementation. ----------------------------------------------------------------------------- void memory::working() { while (true) { wait(SC_ZERO_TIME); wait(SC_ZERO_TIME); if(!request.read()) wait(request.posedge_event()); data = IO_data.read(); /* ... */ } } ----------------------------------------------------------------------------- My problem is that without the 2 wait(SC_ZERO_TIME) statements, a quick fix made some time ago, the data read is wrong (not current cycle). Since I checked that every master is filling first the data field then raising the request signal, I don't understand the need of two delta cycles to avoid reading the old value. Any idea/suggestion? Ciao, Daniele
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