Search the Community

Showing results for tags 'sc_signal'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Synthesizable Subset v1.4 Public Review
    • SystemC Verification (UVM-SystemC, SCV)
  • UVM (Universal Verification Methodology)
    • UVM 1.2 Public Review
    • Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • Simulator Specific Issues
    • UVM Commercial Announcements
  • Portable Stimulus
    • Portable Stimulus Discussion
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • OCP (Open Core Protocol)
  • UCIS (Unified Coverage Interoperability Standard)
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Calendars

  • Community Calendar

Found 9 results

  1. SOLVED: Nevermind, I made some mistakes in calling the wrong methods for writing/reading from ports. Thanks for your attention anyway! I'm trying to implement this example of a memory and a cpu that are communicating. CPU <==> MEM The modules use a single bidirectional data-line for reading/writing. I defined a signal in sc_main: sc_signal<int,SC_MANY_WRITERS> s_memdata; which I connect to the CPU and MEM module through their ports: sc_inout<int> p_memdata; The CPU is writing to the s_memdata signal: p_memdata.write(getrnddata()); As well as the memory: p_data.write( m_data[ m_curAddr ] ); In the debugger I see that the m_curAddr is changing correctly. Yet, the VCD file shows that the signal "data" is not changing when the "address" is changed (as shown in the figure) Actually, the "data" only changes when the cpu is writing to it, not when the memory is. (I was not able to show the function read/write signal because the enum didn't show in the VCD file). It seems to me that there is something going on with the two modules writing to the same channel. I've noticed sc_logic that introduces Z and X values, is this the appropriate way? edit: I've created a simple proof of principle with two writers that talk to a single sc_signal< bool, SC_MANY_WRITERS > which seems to work. So the problem is something different. Thanks for any help or tips. mem_tb.cpp int sc_main(int argc, char* args[]){ Memory * mem; CPU * cpu; mem = new Memory("main_memory"); cpu = new CPU("cpu"); /* sgn */ sc_signal<Memory::Function,SC_MANY_WRITERS> s_memfunc; sc_signal<Memory::RETSignal> s_memsig; sc_signal<int> s_memaddr; sc_signal<int,SC_MANY_WRITERS> s_memdata; sc_clock clk; mem->p_addr(s_memaddr); mem->p_func(s_memfunc); mem->p_data(s_memdata); mem->p_sig(s_memsig); cpu->p_memdata(s_memdata); cpu->p_memaddr(s_memaddr); cpu->p_memsig(s_memsig); cpu->p_memfunc(s_memfunc); mem->clk( clk ); cpu->clk( clk ); std::cout << "Running, CTRL+C to exit..." << std::endl; sc_trace_file * trace = sc_create_vcd_trace_file("trace"); sc_trace(trace, s_memaddr, "addr"); sc_trace(trace, s_memdata, "data"); sc_trace(trace, s_memfunc, "func"); sc_trace(trace, s_memsig, "sig"); sc_start(); sc_close_vcd_trace_file( trace ); return 0; } cpu.h #include <systemc.h> #include "memory.h" #include <boost/random.hpp> SC_MODULE( CPU ) { public: sc_in<bool> clk; sc_in<Memory::RETSignal> p_memsig; sc_out<Memory::Function> p_memfunc; sc_out<int> p_memaddr; sc_inout<int> p_memdata; SC_CTOR( CPU ) { SC_METHOD(exec); sensitive << clk.pos(); dont_initialize(); SC_METHOD(done); sensitive << p_memsig; dont_initialize(); m_waitmem = false; rng.seed( time(NULL) ); dist = new boost::random::uniform_int_distribution<>(0,1<<16); } private: boost::random::mt19937 rng; boost::random::uniform_int_distribution<> *dist; bool m_waitmem; int rand(); Memory::Function getrndfunc(); int getrndaddr(); int getrnddata(); void exec(); void done(); }; cpu.cpp Memory::Function CPU::getrndfunc() { switch( rand() % 2 ) { case 0 : { return Memory::FUNC_READ; } default : { return Memory::FUNC_WRITE; } /* 1, and all other cases... */ } } int CPU::getrndaddr() { return rand() % MEM_SIZE; } int CPU::getrnddata() { return rand(); } int CPU::rand() { return (*dist)(rng); } void CPU::exec() { if(m_waitmem) return; int addr = getrndaddr(); Memory::Function f = getrndfunc(); p_memfunc.write(f); p_memaddr.write(addr); if(f==Memory::FUNC_WRITE) p_memdata.write(getrnddata()); } void CPU::done() { if( p_memsig.read() == Memory::RSIG_NONE ) return; m_waitmem = false; p_memfunc.write(Memory::FUNC_NONE); } memory.h #define MEM_SIZE 512 SC_MODULE( Memory ) { public: enum Function { FUNC_NONE = 0, FUNC_READ = 1, FUNC_WRITE = 2 }; enum RETSignal { RSIG_NONE, RSIG_READ_FIN, RSIG_WRITE_FIN, RSIG_ERR }; sc_in<bool> clk; sc_in<Function> p_func; sc_in<int> p_addr; sc_inout<int> p_data; sc_out<RETSignal> p_sig; SC_CTOR( Memory ){ SC_METHOD(execute); sensitive << clk.neg(); m_clkCnt = 0; m_curAddr = 0; m_curData = 0; m_curFunc = Memory::FUNC_NONE; m_data = new int[MEM_SIZE]; m_writesCnt = 0; m_readsCnt = 0; m_errorsCnt = 0; m_errorCode = 0; } ~Memory(); private: int m_clkCnt; int m_curAddr; int m_curData; Function m_curFunc; int* m_data; int m_errorCode; int m_writesCnt; int m_readsCnt; int m_errorsCnt; RETSignal read(); RETSignal write(); void execute(); }; memory.cpp #include "memory.h" Memory::~Memory() { delete[] m_data; } Memory::RETSignal Memory::read() { if( m_errorCode ) { m_errorsCnt++; return RSIG_ERR; } p_data.write( m_data[ m_curAddr ] ); m_readsCnt++; return RSIG_READ_FIN; } Memory::RETSignal Memory::write() { if( m_errorCode ) { m_errorsCnt++; return RSIG_ERR; } m_data[ m_curAddr ] = m_curData; m_writesCnt++; return RSIG_WRITE_FIN; } void Memory::execute() { if( m_curFunc != FUNC_NONE ) { m_clkCnt++; if( m_clkCnt == 100 ) { RETSignal retSig = RSIG_ERR; switch(m_curFunc){ case FUNC_READ : { retSig = read(); break; } case FUNC_WRITE : { retSig = write(); break; } default : { /* */ } } p_sig.write( retSig ); m_clkCnt = 0; m_curFunc = FUNC_NONE; } return; } if( p_func == FUNC_NONE ) return; m_curFunc = p_func.read(); m_curAddr = p_addr.read(); m_curData = p_data.read(); p_sig.write( RSIG_NONE ); }
  2. Hi, I want to pass a sc_signal (the reference of one) of any type to a class as a CTOR-argument. Since i found out, that the &-Operator of the class sc_signal<T> is overloaded, so i don't get the reference of an sc_signal<T> object but instead i get a reference to an Object of type T. How am i supposed to pass an sc_signal<T> to a function or a class? Example-Code: #include <systemc.h> template<typename T> class TInput{ public: typedef sc_signal<T> &TMember; TInput(TMember member):member(member){} // some functions which use member private: TMember member; }; int sc_main(int argc, char** argv){ sc_signal<sc_uint<12> > signal1("signal1"); TInput<sc_uint<12> > input(signal1); // here is the problem, because &signal1 does not return return 0; // its own reference but a const reference to its member // so the compiler is telling me, that i want to call a function which does not exist } here is a link to sc_signal class of systemc lysium documentation http://www.iro.umontreal.ca/~lablasso/docs/SystemC2.0.1/html/classsc__signal.html especially this function operator const T & () const its implementation (of sc_logic) can be found under following link: http://www.lysium.de/docs/systemc-2.2/docs/html/sc__signal_8h-source.html 00132 operator const T& () const 00133 { return read(); } 00113 // read the current value 00114 virtual const T& read() const 00115 { return m_cur_val; } 00648 sc_dt::sc_logic m_cur_val; // current value of object. I hope there is any solution to my problem and thanks in advance.
  3. I am trying to get an interface binded with a vector of port declared as sc_vector<sc_in<bool> > : std::vector<sc_object*> children = get_child_objects(); sc_signal<bool> *s = NULL; const char *tmp = "sc_vector"; for (unsigned i = 0; i < children.size(); i++) { if (strcmp(nm, children->basename()) == 0) { if (strcmp(children->kind(), tmp) == 0) { sc_vector<sc_in<bool> > *v = dynamic_cast<sc_vector<sc_in<bool> > * > (children); if (v != 0) { s = dynamic_cast<sc_signal<bool> *> (&v->at(0)); } } } } In the above code, I got the value of s as NULL. I have binded a port with signal, but still it's unexpected behavior. Am I doing something wrong here ??
  4. Hi Folks What is the difference in default_event() and value_changed_event() for sc_signal channel. I have an sc_in port in my module and a process run is sensitive on it SC_THREAD(run) sensitive<<irq; When the run will be activated - when there any any event on irq (read or write) - when there is some value change event When I use SC_THREAD(run) sensitive<<irq.value_changed_event(); or SC_THREAD(run) sensitive<<irq.default_event(); I get the following error Error: (E112) get interface failed: port is not bound: port 'initiator.irq' (sc_in) In file: ../../../../systemc-2.3.0/src/sysc/communication/sc_port.cpp:230 Regards RahulJn
  5. Dear All, I created a class BusAssembly, which basically contains a matrix of sc_uint<>, and I provided it with operator= , ==, >> and sc_trace. In a simple sc_main I defined some variables with type sc_signal<BusAssembly<W,Dim0,Dim1> > . Then I assinged them with a static matrix. (Both by = or .write()) Now, the new_value of the sc_signal variables is correctly assigned, but after a while of simulaiton, their current value is not updated to it. Surprisingly it is only working for the fisrt assignment occurrence. SystemC 2.3.1-Accellera --- Sep 20 2014 12:00:32 Copyright (c) 1996-2014 by all Contributors, ALL RIGHTS RESERVED data1 (5,1,1,1,1,1) name = signal_0 value = (5,1,1,1,1,1) new value = (5,5,3,1,2,3) data2 (1,1,1) name = signal_1 value = (1,1,1) new value = (1,64,130) data1 (5,5,3,1,2,3) <-- After simulation data1 is OK name = signal_0 value = (5,5,3,1,2,3) new value = (5,0,0,0,0,0) data2 (1,1,1) <-- data2 is not name = signal_1 value = (1,1,1) new value = (1,0,0) data1 (5,5,3,1,2,3) <-- data1 is not name = signal_0 value = (5,5,3,1,2,3) new value = (5,0,0,0,0,0) data2 (1,1,1) <-- neither data2 name = signal_1 value = (1,1,1) new value = (1,0,0) What am I mistaken with ? Thank you in advance. Please find here the sc_main code: #include <iostream> #include "frames.h" using namespace std; int sc_main(int argc, char *argv[]) { // Testbench internal variables static const sc_uint<4> a[5][1] = {{5},{3},{1},{2},{3}}; static const sc_uint<4> b[5][1] = {{0},{0},{0},{0},{0}}; static const sc_uint<8> c[1][2] = {{64,130}}; static const sc_uint<8> d[1][2] = {{0,0}}; sc_signal<BusAssembly<4,5> > data1; sc_signal<BusAssembly<8,1,2> > data2; sc_clock clk("clk",10,SC_NS,true); data1.write(a); cout << "data1 " << data1 << "\n"; data1.dump(); data2.write(c); cout << "data2 " << data2 << "\n"; data2.dump(); sc_start(20,SC_NS); data1 = b; cout << "data1 " << data1 << "\n"; data1.dump(); data2 = d; cout << "data2 " << data2 << "\n"; data2.dump(); sc_start(20,SC_NS); data1.dump(); data2.dump(); return EXIT_SUCCESS; } And the Class definition one "frames.h" : #include <exception> #include "systemc.h" #include <stdio.h> template <int W=8, unsigned short Dim0=1, unsigned short Dim1=1> class BusAssembly { private: static const unsigned short dim = Dim0; public: sc_uint<W> value[Dim0][Dim1]; BusAssembly() { for (unsigned short i=0; i<Dim0; i++) for (unsigned short j=0; j<Dim1; j++) value[i][j] = 1; } BusAssembly(const sc_uint<W> t[][Dim1]) { for (unsigned short i=0; i<Dim0; i++) for (unsigned short j=0; j<Dim1; j++) value[i][j] = t[i][j]; } // Assignment operator BusAssembly& operator = (const BusAssembly& v) { if (this == &v) return *this; if (dim == v.dim) { for (unsigned short i=0; i<Dim0; i++) for (unsigned short j=0; j<Dim1; j++) value[i][j] = v.value[i][j]; // cout << *this << "\n"; return *this; } else throw "Assignment Error: Dimensions must match!"; } bool operator == (const BusAssembly& v) const { bool end = true; if (dim == v.dim) { for (unsigned short i=0; i<Dim0 && end; i++) for (unsigned short j=0; j<Dim1 && end; j++) end = (value[i][j] != v.value[i][j]); return end; } else throw "Assignment Error: Dimensions must match!"; } inline friend void sc_trace (sc_trace_file *tf, const BusAssembly& v, const std::string& NAME) { // sc_trace(tf,v.dim, NAME + ".dim"); for (unsigned short i=0; i<Dim0; i++) for (unsigned short j=0; j<Dim1; j++) { std::stringstream str; str << NAME << ".value(" << i << ")(" << j << ")"; sc_trace(tf,v.value[i][j],str.str()); } } inline friend ostream& operator << (ostream& os, const BusAssembly& v) { os << "(" << v.dim ; for (unsigned short i=0; i<Dim0; i++) for (unsigned short j=0; j<Dim1; j++) os << "," << v.value[i][j]; os << ")"; return os; } };
  6. Hi all, I am creating some sc_signal<vector<T> > ports with a user defined T. I have already found a proper link for the same (answer provided by AR/Ravi, inheriting from STL vector). http://www.accellera...g=msg00004.html But now my question is, I am defining other ports where T will be sc_bv, double etc. So shall I write above code for each of the variable type or is it ok with all? (I am particularly worried about << and ==). Thank you. P.S. Will next IEEE1666 talk about sc_vector? Will some provision for above scenario provided in later versions?
  7. Hi, I have a set of signals defined as: sc_signal<sc_logic> bit0; sc_signal<sc_logic> bit1; sc_signal<sc_logic> bit2; I have another buses defined as sc_signal<sc_bv<3> > bus_input; sc_signal<sc_bv<3> > bus_output; I would like to do this operation: bus_output = bit(i) & bus_input where i = 0,1,2 For this, I am writing this code: bus_output = (bit2.read(), bit1.read(), bit0.read()) & bus_input.read(); But this does not work. Compile is fine but only the bus_output[0] is correctly being written. other bits are not getting updated. Can you please let me know what is the issue? Thanks, Sachin
  8. How to output "float (double)" from sc_fixed type class using sc_trace? I have an existing model (all in floating point design, using "sc_signal<double>"), and am trying to convert it to its fixed point one (i.e. using sc_signal<sc_fixed< ,,,, > >"). sc_signal<double> ch_a; sc_signal<sc_fixed<16,8, SC_RND, SC_SAT> > ch_a_fix; sc_trace(tf, ch_a, "ch_a" ); // floating point channel tracing, it traces signal in "double". sc_trace(tf, ch_a_fix, "ch_a_fix ); // fixed point channel tracing: it traces signal in "integer numbers". The question is, how can I trace the sc_fixed type class (sc_signal<sc_fixed<...:> >) in floating point numbers? For waveform viewer-wise, I'm using gtkwave for now. I have found one posting that has the same question that I have now. But it doesn't have any replies there. http://www.accellera.org/Discussion_Forums/helpforum/archive/msg/msg?list_name=help_forum&monthdir=200802&msg=msg00035.html Many thanks in advance.
  9. Hi, everybody. I'm needing use netbeans IDE to develop systemC projects on windows 7. I installed the netbeans 7.3 and the cygwin with gcc 4.8. the systemC already be installed and working normally in cygwin (I already have used...). recently, I installed systemC on netbeans, that use cygwin compiler, and I can use normally too: netbeans "recognize the systemC language", compile and execute my projects. my only problem is that, on netbeans, the "sc_signal<bool>" is don't recognize. =S the "sc_signal<int>" work, "sc_signal<sc_logic>" work and all the others.... the code with "sc_signal<bool>" compile normally on the netbeans, but the signal of this type is always underlined in red, indicating an error. the problem is on netbeans, because the code compile without any error (with gcc of the cygwin)... on netbeans appear "Unable to resolve the identifier 'write'" (for example). can anyone help me? (if nobody understand, I can detail) sorry my english errors and thanks a lot.