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Found 1 result

  1. Hi, I'm trying to write generic 3-state buffer with method of the module as follows: note that 'output' is an sc_signal_rv<n> defined in the module's body. The problem is that the red section fails compilation because bit accessing is prohibited. Is the other way to set "all Z" when the resolved-signal width is a parameter n???? hope someone can help... V template <class T1, unsigned n, class T3> void bus3state_unit<T1,n,T3>::thread0(void) { T1 input ; input = in.read() ; for(int i=0;i<n;i++) output.write('Z') ; if( enable.read() ) { output.write(input) ; } out.write(output) ; }
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