Jump to content

Search the Community

Showing results for tags 'reset'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI (Configuration, Control & Inspection)
    • SystemC Datatypes
  • UVM (Universal Verification Methodology)
    • UVM 2017 - Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • UVM Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM (Pre-IEEE) Methodology and BCL Forum
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus Pre-Release Discussion
    • Portable Stimulus 1.0
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • OCP (Open Core Protocol)
  • UCIS (Unified Coverage Interoperability Standard)
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests


Biography


Location


Interests


Occupation


Company

Found 4 results

  1. Hi everyone, For a processor model, I need to be able to reset or kill a transaction sent across an interface and stored in a Payload Event Queue. How can I do that? If I initiate a transaction like this : tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; tlm::tlm_phase* trans_phase = new tlm::tlm_phase; sc_time* delay = new sc_time; tlm::tlm_sync_enum* transStatus = new tlm::tlm_sync_enum; *trans_phase = tlm::BEGIN_REQ; *delay = SC_ZERO_TIME; // Or any delay trans->set_command(tlm::TLM_WRITE_COMMAND); trans->set_dmi_allowed(false); trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); *transStatus = InitSocket.nb_transport_fw(*trans, *trans_phase, *delay); How could I, afterwards and before the specified delay has elapsed, kill this transaction or remove it from the target Payload Event Queue? Can I keep a copy of the 'trans' pointer to reset the transaction content if needed? Thank you for your help! Regards, J-B
  2. Hi, I am implementing multiple reset inside UVC componenets (sequencer, driver, monitor and etc). When reset is asserted between get_next_item() and item_done(), the following error is issued. UVM_ERROR (SEQREQZMB) The task responsible for requesting a wait_for_grant on sequencer '....' for sequence '...' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues. I guess this error is caused that queue for sequence item already gets a item to transfer into driver. How can I fix this problem? How can I remove current item from the arbitration queue? My UVC is using run_phase(). I don't use main_phase(). So, I would like to control it using run_phse(). Thanks & Regards,
  3. Resetting a randc permutation sequence (See attached page from 1800-2012 SystemVerilog spec.) function bit [16:0] get_reasonable_buggy_data(bit [(A_SIZE-1):0] rid); string where="buggy"; // randc unsigned int picky; //random-cyclical variable DECLARED ABOVE IN CLASS, SUCH // void'(randomize(pick) with {pick==1;}); FAILED-ATTEMPT to recompute permutation sequence for (int i=0; i<4; i++) begin if (!randomize(picky) with {picky>=0; picky<4;}) begin `uvm_fatal("FAIL","") end `uvm_info(where,$psprintf("i=%0d picky=%0d data[1:0]=%2b",i, picky, rdata_set[picky][1:0]),UVM_HIGH) if ( rdata_set[picky][1:0] == 2'b11 ) begin `uvm_info(where,$psprintf(" data[1:0]=%2b. GOT IT!",i, rdata_set[picky][1:0]),UVM_HIGH) return(rdata_set[picky]); //exit random-cyclical sequence here. How to start it over? end end `uvm_fatal(where,$psprintf("After cycling thru entire memory model, did not find data desired")) endfunction In a function, I am cycling thru the randomized values of a randc variable, "picky", which is used as an index. I find what I am looking for and stop, not completing the cycle thru all the possible values of the variable, in a given permutation sequence. Returning to this function, the randomization of the randc, picks up where the previous permutation sequence left off. This makes sense. This is undesirable here and leads to problems**. I want to reset the randc permutation sequence, but am not sure if I am just not doing it properly or if my simulator does not support it properly. (I can ask the simulator vendor about the latter. I am inquiring here about the former.) Problem details: The randc variable "picky" can have 4 values: 0,1,2,3. We call the above function 3 times. Each time we want to use picky as an index to randomly search a memory of size 4, stopping when we find what we want. Permutation sequences of picky are: 1st: 0,2,3,1 2nd: 3,0,1,2 3rd: 0,.... //final 3 are irrelevant and sim dies before we get to them First time function is entered, we select '0','2',and '3' and find the goal in #3 and function returns. Second time we finish off the 1st permutation with '1' and go into 2nd with '3', and have found what we want in #3. Function returns. Third time, we finish the 2nd permutation with '0', '1', '2', and continue into the 3rd with '0'. Function fails. So, we did not get the randc effect we wanted, we never got to #3. Even though we were iterating 4 times, once for each memory location and using a randc, we got a duplicate, b/c our randomization straddled two permutation sequences. As such, we never found #3. Print output from simulation: [buggy] i=0 picky=0 data[1:0]=00 [buggy] i=1 picky=2 data[1:0]=00 [buggy] i=2 picky=3 data[1:0]=11 [buggy] data[1:0]=10. GOT IT!3 [buggy] i=0 picky=1 data[1:0]=00 [buggy] i=1 picky=3 data[1:0]=11 [buggy] data[1:0]=01. GOT IT!3 [buggy] i=0 picky=0 data[1:0]=00 [buggy] i=1 picky=1 data[1:0]=00 [buggy] i=2 picky=2 data[1:0]=00 [buggy] i=3 picky=0 data[1:0]=00 [buggy] After cycling thru entire memory model, did not find data desired Note, this is a contrived example. I could allow all permutation sequences to complete or resolve this another way. Based upon the description in the spec page attached, I tried to reset the permutation sequence by inserting the line labelled "FAILED-ATTEMPT". Is that how resetting a permutation sequence should work? Note: I am using IUS 13.10-s006
  4. I'm attempting to do some performance analysis of a network-on-a-chip I've created in SystemC. To do this, I want to automate multiple simulation runs so that I can find max/min/mean/variance of the values I am interested in. My original idea was to simply wrap my main.cpp (the code that constructs the network out of modules and signals and begins the simulation) in a "for" loop and run through it x number of times. However, I am currently encountering error E113 after running through the "for" loop just once, which indicates that SystemC doesn't allow me to reconstruct the network while a simulation is running (understandably). So, my question is now: How can I completely stop and reset my simulation environment at the end of my "for" loop to allow it to just do its thing x number of times? Thanks in advance.
×