Search the Community

Showing results for tags 'randomization'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Synthesizable Subset v1.4 Public Review
    • SystemC Verification (UVM-SystemC, SCV)
  • UVM (Universal Verification Methodology)
    • UVM 1.2 Public Review
    • Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • Simulator Specific Issues
    • UVM Commercial Announcements
  • Portable Stimulus
    • Portable Stimulus Discussion
  • IP-XACT
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • OCP (Open Core Protocol)
  • UCIS (Unified Coverage Interoperability Standard)
  • Commercial Announcements
    • Announcements

Categories

  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption

Calendars

  • Community Calendar

Found 3 results

  1. Hi All, Just wanted to check if the UVM sequence macros (UVM_DO_ON_WITH and UVM_DO_WITH) which support randomizing the sequence object are yet supported by UVM-SC or not? If not, what is the best way to add some randomization in the framework? I saw a post where there are some snippets (link given below) using scvx_rand_object class but I am not sure where to find this(didn't find it in latest SCV and UVM-SC libraries). http://nascug.org/events/20th/1-NASCUG20-UVMforSystemC-Karsten.pdf Also, I get errors while using plain UVM_DO_ON macros. Is it expected? The same works fine with ahb_wr_seq->start(top_env->agent->ahb_sequencer_inst); I have registered the sequence class with factory already. UVM_DO_ON(ahb_wr_seq,top_env->agent->ahb_sequencer_inst); Error message says: /nfs/iind/disks/ba_bdl_xplore_disk001/am5/UVM_SC/uvm-systemc-1.0-alpha1/src/uvmsc/macros/uvm_sequence_defines.h:150:31: error: expected type-specifier before ‘typeof’ SEQ_OR_ITEM = dynamic_cast< typeof(SEQ_OR_ITEM) >(create_item(objw__, SEQR, "SEQ_OR_ITEM")); ^ /nfs/iind/disks/ba_bdl_xplore_disk001/am5/UVM_SC/uvm-systemc-1.0-alpha1/src/uvmsc/macros/uvm_sequence_defines.h:115:3: note: in expansion of macro ‘UVM_CREATE_ON’ UVM_CREATE_ON(SEQ_OR_ITEM, SEQR) \ ^ /nfs/iind/disks/ba_bdl_xplore_disk001/am5/UVM_SC/uvm-systemc-1.0-alpha1/src/uvmsc/macros/uvm_sequence_defines.h:80:3: note: in expansion of macro ‘UVM_DO_ON_PRI_WITH’ UVM_DO_ON_PRI_WITH(SEQ_OR_ITEM, SEQR, -1, "") ^ ahb_basic_test.h:59:11: note: in expansion of macro ‘UVM_DO_ON’ UVM_DO_ON(ahb_wr_seq,top_env->agent->ahb_sequencer_inst); Appreciate any help here. Thanks Akhila
  2. Hi All, I am seeing following error when I try to assign array values using inline constraints Array size's and dimensions are same and array slicing is not there ,but still I see below error. Can somebody please through light on this error? Also suggest best practices class A_seq extends uvm_sequence #(id_nfc_tx_transfer); `uvm_object_utils(A_seq) `uvm_declare_p_sequencer(tx_sequencer) bit [7:0] data_byte[`MAX_DATA:0] ; function new(string name="A_seq"); super.new(name); endfunction virtual task body(); ///Array Initialization for (int i=0;i<=5;i++) data_byte= 'hAB; `uvm_do_with(req,{ tx_bit_rate_sel ==212; tx_num_of_bytes == 5; tx_data_byte == data_byte; }) endtask endclass Error :Randomization constraint has this error, which will cause the randomize function to return 0 and no new rand values will be set: Slices of unpacked arrays are not currently supported in this context
  3. I was just reading the 1800-2012 standard and I've come across something that strikes me as a possible contradiction. In section 18.8 Disabling random variables with rand_mode() it states that Later on, when an example is presented, I see the following code snipped: The comment states that packet_a.rand_mode(0) disables randomization for all variables inside the object, which is against the statement from above. Could anyone who's part of the SV committee shed some light on the issue?