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ljepson74 posted a topic in UVM SystemVerilog DiscussionsQ1) I'd like confirmation that the following waits for a posedge of clk are identical. (The code it refers to is far below.) 1) @(posedge my_play_if.clock); or @(posedge clk); 2) @(my_play_if.cb1); Q2) I'd also like to confirm that input and output clocking_skew of a clocking block have no effect on the inputs of the interface. They only affect the inputs and outputs of that clocking block. I'm pretty confident about both of these and the SystemVerilog LRM seems clear, but I want to confirm while I am cleaning up some inherited code which is not currently working. Reference: SystemVerilog Standard 1800-2012.pdf, Section "14. Clocking blocks" Below is some sample code I was hacking around with. //Interface, clocking blocks, and waiting for clock edge interface play_if(input bit clock); clocking cb1 @(posedge clock); default input #2 output #2; //clocking_skew is irrelevant to interface inputs, right? endclocking endinterface module top; bit clk; play_if my_play_if(.clock(clk)); always #5 clk=~clk; initial begin $monitor($time," clk=%1b",clk); clk=1; #100 $finish; end task tclk(); $display($time," pre-clk"); @(posedge my_play_if.clock); $display($time," post-clk"); endtask task tcb1(); $display($time," pre-cb1"); @(my_play_if.cb1); $display($time," post-cb1"); endtask initial begin #23; $display($time," --------------START"); tclk(); @(posedge my_play_if.clock); tclk(); #3; tcb1(); tcb1(); @(posedge my_play_if.clock); tcb1(); tclk(); tcb1(); #3; @(posedge my_play_if.clock); $display($time," --------------FINISH"); end endmodule : top