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Found 4 results

  1. Hi, I was trying to map port from a outer module to an input port of inner module. The ports to be mapped in a certain way that a range of input port of outer module is to be mapped with the input port of the inner module. Example is given below. inner module : SC_MODULE(alu) { sc_in<sc_uint<8> > a_in; sc_in<sc_uint<8> > b_in; sc_in<sc_bv<2> > op; sc_in<bool> en; sc_out<sc_uint<8> > out_sig; void calc_out(); SC_CTOR(alu){ cout<<"alu constructor"<<endl; SC_METHOD( calc_out ); sensitive<<op<<a_in<<b_in<<en; } }; Outer module: sc_in <sc_uint<24> > ins; sc_in <bool> coack; sc_in <bool> memack; sc_out <sc_uint<8> > out; sc_out <sc_uint<8> > memout; sc_out <sc_uint<23> > coprout; sc_out <bool>corqst; sc_out <bool> memrqst; sc_signal <bool> aluen ; //sc_signal <sc_bv<24> > ins_sig; sc_signal <sc_int<8> > result_sig; alu* alup; SC_CTOR(processor) { alup = new alu("alup"); alup->a_in(ins.range(15,8)); // HERE THE ERROR IS COMMING. I want to map a range of port bit of processor (outer // int i; // module) to the whole one port of alu (inner module) // alup->a_in[7](ins[15]); // for(i=15;i>=8;i--) // alup->a_in[i-8](ins); alup->b_in(ins_sig.range(7,0)); // SAME HERE // for(i=7;i>=0;i--) // alup->b_in(ins); alup->op(ins_sig.range(17,16)); //SAME HERE for(i=17;i>=16;i--) alup->op[i-16](ins); alup->en(aluen); alup->out_sig(result_sig); SC_THREAD(request_copr); sensitive << ins << coack.pos(); SC_THREAD(request_mem); sensitive << ins << memack.pos(); SC_METHOD(show_out); sensitive<<out_sig; } // functions.... } I will be highly thankful if anyone ca help me with this.
  2. Hi all, I have been trying to do something that I'm not sure it's possible. I have some TDF modules that are connected to each other by sca_in and sca_out ports. All of this modules will have at least one of each in/out ports. My idea was that maybe some of them will have some extra in/out ports. For example, if I want two TDFs outputs to go to one TDF input, it is not possible using just one port. Instead, those TDF modules would have a vector of sca_in's so, if I need an extra port, this will be initialized and bound to a signal. All this is already done and compiling. My problem is that when I initialize and bind that new port, it is not specifically assigned to a TDF so I get this error: "Error: (E100) port specified outside of module: port 'sca_tdf_in_0' (sc_port_base)". I understand the reason of this error, but I would like to know if it is possible to assign this port to its TDF. Here I will show my code, maybe it's helpful. class 'gen' is a generator of doubles. It sends an increasing double through its 'out' port. class 'pass' is just getting whatever comes from its 'in' port and sending it out through its 'out' port. class 'waste' is where the 'magic' may be. Receives whatever which is coming from 'pass'. main.cpp: #include <systemc-ams> #include "gen.h" #include "waste.h" #include "pass.h" int sc_main(int argc, char *argv[]) { gen g("g"); pass p("p"); pass p2("p2"); waste w("w"); sca_tdf::sca_signal<double> sig("sig"); sca_tdf::sca_signal<double> sig2("sig2"); sca_tdf::sca_signal<double> sig3("sig3"); g.out(sig); p.in(sig); // Both 'p' and 'p2' receive from the same signal 'sig'. p2.in(sig); // This works perfectly. p.out(sig2); // The out port of both are bound to different signals. p2.out(sig3); // Otherwise, I would get an error. w.in(sig2); // This is a normal binding (to 'p' and 'sig') that works just fine. w.bind(sig3); // Here's where I want to implement my idea. Look at 'waste.h' sc_core::sc_start(500.0, sc_core::SC_MS); sc_core::sc_stop(); return 0; }; waste.h: #ifndef WASTE_H #define WASTE_H #include <systemc-ams> #include <vector> SCA_TDF_MODULE(waste) { sca_tdf::sca_in<double> in; // Main 'in' port std::vector<sca_tdf::sca_in<double>*> secondary_ins; // Vector of extra 'in' ports std::vector<sca_tdf::sca_in<double>*>::iterator it; // Iterator int ins; // Number of extra 'in' ports SCA_CTOR(waste) { it = secondary_ins.begin(); ins = 0; } // This initializes the extra 'in' port and adds it to the vector // Here should go the 'assignation' if it is possible. void new_in() { sca_tdf::sca_in<double> *sec_in = new sca_tdf::sca_in<double>(); secondary_ins.insert(it, sec_in); ins++; } // This method is called in 'main.cpp' and it might assign // the new 'in' port to the given signal void bind(sca_tdf::sca_signal<double> &s) { new_in(); secondary_ins.at(secondary_ins.size()-1)->bind(s); } void processing() { double d = in.read(); std::cout << name() << " - main_in : " << d << std::endl; for(int i=0; i<secondary_ins.size(); i++) { double d2 = secondary_ins.at(i)->read(); std::cout << name() << " - sec_in(" << i << "): " << d2 << std::endl; } } }; #endif So basically that's it. Any ideas? Is it even possible? Thanks a lot
  3. May a module or interface have default 'no-connect' port connections, for ports that we don't need to connect? I need to use an interface which is shared between testbenches. I instantiate it a lot and don't use many of the ports (i.e. they can be 'no connects') Using Cadence irun, I get this warning when I don't connect inputs to the interface: ncelab: *W,CUVWSI With tasks/functions, I can have a default value for an input argument. Is there anything similar for interfaces (or modules for that matter)? Rather than creating a bunch of dummy inputs for these ports that are not relevant to me, I'd like to change the interface somehow to clear up the warnings for cases where I don't want to use them. trying to clean up some warnings, thanks Note: the interface inputs mentioned are being used for a small piece of internal control logic in the interface. I suppose someone might suggest using parameterized interfaces. I don't recall offhand, but believe there is a reason that we are not using a parameterized interface for this. I'll have to check with the original developer.
  4. Hi, experts, There is several drivers and one subscriber. I put one uvm_analysis_port in each driver and several imps in the subscriber via using macro `uvm_analysis_imp_decl(_a), `uvm_analysis_imp_decl(_b, etc. Also Implement functions write_a(), write_b(), etc. write_a() and write_b() have different processing logic. Then, the uvm_analysis_port in each driver invokes one of the functions write_a(), write_b(), etc. But the VCS reports such an error: Could not find member 'write_a' in class 'uvm_analysis_port', at "/EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/tlm1/uvm_analysis_port.svh", Is there anybody to handle my problem? Thanks in advance!
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