Jump to content

Search the Community

Showing results for tags 'port delegation'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI Public Review
  • UVM (Universal Verification Methodology)
    • Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • Simulator Specific Issues
    • 1800.2-2017 Early Adopter Release
    • UVM Commercial Announcements
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus Discussion
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • OCP (Open Core Protocol)
  • UCIS (Unified Coverage Interoperability Standard)
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption


  • Community Calendar

Found 1 result

  1. Hi Folks Is it allowed to connect an initiator port to a target port up in the hierarchy ? Is it allowed to connect an target port to a initiator port up in the hierarchy ? I assume no but what I observe that OSCI systemc implementation allows this. I tried to reproduce this problem with a small example(attached) where I have a component model with following ports tlm_utils::multi_passthrough_initiator_socket<model,32, tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> master; tlm_utils::multi_passthrough_target_socket<model,32, tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> slave; Then I create a subsystem with an instance of above component model and a following port tlm_utils::multi_passthrough_initiator_socket<model,32, tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> master; Then if I connect model_inst->master.bind(master); // this is fine master.bind(model_inst->slave); // this should not allowed, I think I am attaching the complete code. Can you help me to understand whether it is allowed ? Thanks Sumit test.cpp