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raiyyanfaisal09 posted a topic in UVM SystemVerilog DiscussionsI am new to Synopsys VCS. I have been trying to simulate the testbench developed in UVM using VCS in command mode (Linux environment). But, I am not able to get the info displays and the output displays. I am have written the makefile using perl scritps. Can soemeone please tell me where I can find the detail example of using the options in my makefile to run it succesfully while viewing the output displays in command mode