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Showing results for tags 'parameterized'.
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mrforever posted a topic in UVM (Pre-IEEE) Methodology and BCL ForumHi, all I want to use the factory mechanism to write one reusable test, this is the codes class my_test #(parameter TSID=0) extends uvm_test; typedef my_test #(TSID) this_typ; typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; static function type_id get_type(); return type_id::get(); endfunction : get_type function new(string name = "my_test", uvm_component parent=null); super.new(name,parent); endfunction : new ... endclass But I met such a compile error: Error-[NCE] Non-constant expression The following expression should be a constant. Expression: $sformatf("my_test%0d", TSID) Source info: typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; ... If the second parameter should be a constant or constant expression in typedef uvm_component_registry #(my_test #(TSID), $sformatf("my_test%0d", TSID)) type_id; then how can i distinguish the specialized test using TSID which is from run option (my original idea is that using parameter TSID to distinguish the different specialized test)? Second problem, my_test is a generic class now, where should the specialized test define and how to define if my original idea is feasible? Regards
caowangyang posted a topic in UVM SystemVerilog DiscussionsHi, Dear All, I have a very interesting problem here, image a multiple lanes (changeable) communication system, since some relationship maybe exist across those lanes, in order to model it, I just use a parameterized driver/sequencer in a verification environment, which looks like as: class driver #(parameter LANES = 4) extends uvm_driver #(transaction #(LANES)); class sequencer #(parameter LANES = 4) extends uvm_sequencer #(transaction #(LANES)); Simultaneously, I want to use following Macro in my sequence providing a handle pointed to the sequencer, as we know, called p_sequencer. class pma_base_sequence #(parameter LANES = 4) extends uvm_sequence; `uvm_declare_p_sequencer(sequencer #(LANES)) However, I got following runtime uvm_fatal error: UVM_FATAL ../src/uvc/PMA/pma_sequence_lib.sv(15) @ 0: uvm_test_top.pma_agt.pma_seqr@@pma_base_seq [DCLPSQ] testbench_top.pma_base_sequence.m_set_p_sequencer uvm est_top.pma_agt.pma_seqr.pma_base_seq Error casting p_sequencer, please verify that this sequence/sequence item is intended to execute on this type of sequencer It looks like the casting from my parameterized sequencer above to specific p_sequencer failed, i.e. this statement failed: $cast(p_sequencer, sequencer#(LANES)) I have no idea what's going on here, does anyone knew it ? I really appreciate if you can help me, thanks in advance !