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Hello, I've scoured the internet and this forum for what I imagine will have a very simple solution. Apparently I am not describing it sufficiently. I have a SystemC model comprised of a handful of registers, and single memory bank. I would like to implement TWO blocking transport interfaces to this model. If I implement a single blocking transport ( via inheritance of b_transport ), the method has access to all the model resources. If I want two b_transport interfaces, I've had to move them to channels, which are then instantiated in the model. These channels do not have access to the model resources of course, because they are declared seperately from the model. They communicate transactions to the model via an event (or using a fifo). Therefore, the blocking transport will issue a wait(sc_zero_time) for the transaction to reach the model and perform some action. *Perhaps this solution is already what I should be doing. However, I like the idea of a blocking transport actually setting the value and returning (with no wait statements); but, I cannot do this because I need TWO of these methods. Brian
mrforever posted a topic in UVM (Pre-IEEE) Methodology and BCL ForumHi, experts, I met such a problem. Here are the codes and the vcs reports: -------codes-------- class my_env extends uvm_env; my_sub_env subenv; ... // build phase function void build_phase(uvm_phase phase); ... subenv=new; for (int i =0; i <10; i++) begin subenv = my_sub_env::type_id::create(sformatf("subenv%0d", i), this); end ... endfunction: build_phase // connect phase function void connect_phase(uvm_phase phase); ... foreach(subenv) begin reg_R.a_map.set_sequencer(subenv.v_sqr.cfg_sqr, reg2apb); end ... endfunction: connect_phase endclass: my_env class my_sub_env extends uvm_env; vsequencer v_sqr; ... function void build_phase(uvm_phase phase); ... v_sqr = vsequencer::type_id::create("v_sqr", this); ... endfunction: build_phase ... endclass: my_sub_env -------reports-------- The vcs reports such an error: UVM_FATAL /EDA_Tools/synopsys/vcs1209/etc/uvm-1.1/uvm-1.1c/src/base/uvm_component.svh(1744) @ 0: v_sqr [CLDEXT] Name 'v_sqr' is not unique to other top-level instances. If parent is a module, build a unique name by combining the the module name and component name: $sformatf("%m.%s","v_sqr"). How can I build a unique name when the parent isn't a module. I mean I cann't build a unique name because there is only one v_sqr in class my_sub_env. I have built a unique name for each subenv, that is sformatf("subenv%0d", i). Does the reports mean that each object should have a unique name when there are multiple subenvs? Could anybody help me to solve this problem? Thanks in advance.