Jump to content

Search the Community

Showing results for tags 'latency'.

More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


  • Accellera Systems Initiative
    • Information
    • Announcements
    • In the News
  • SystemC
    • SystemC Language
    • SystemC AMS (Analog/Mixed-Signal)
    • SystemC TLM (Transaction-level Modeling)
    • SystemC Verification (UVM-SystemC, SCV)
    • SystemC CCI Public Review
  • UVM (Universal Verification Methodology)
    • Methodology and BCL Forum
    • UVM SystemVerilog Discussions
    • Simulator Specific Issues
    • UVM Commercial Announcements
    • UVM 1.2 Public Review
  • Portable Stimulus
    • Portable Stimulus Discussion
    • IP-XACT Discussion
  • IEEE 1735/IP Encryption
    • IEEE 1735/IP Encryption Discussion
  • OCP (Open Core Protocol)
  • UCIS (Unified Coverage Interoperability Standard)
  • Commercial Announcements
    • Announcements


  • SystemC
  • UVM
  • UCIS
  • IEEE 1735/IP Encryption


  • Community Calendar

Found 1 result

  1. Hi all, I guess this is a basic question but I can't find the answer. I have a SystemC module that performs several complex arithmetic operation ( several multiplication ). When I simulate it I can see it performs all those operations in on clock cycle after I provided the input. I'm pretty sure that when I'll feed the HLS tool, the tool will pipeline the operation adding latency. Is there any way to manually add latency in order to match what I guess will be the result of the HLS ? I guess I can simulate the latency changing the SC_METHOD with a SC_THREAD and adding a sort of counter, but I was wondering if there is a more elegant and native way to do it. Cheers.